MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 16
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MAX8770GTL+T
Manufacturer Part Number
MAX8770GTL+T
Description
IC CTLR PS 2/1PH QUICK PWM 40QFN
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX8770GTLT.pdf
(47 pages)
Specifications of MAX8770GTL+T
Applications
Controller, Intel IMVP-6
Voltage - Input
4 ~ 26 V
Number Of Outputs
1
Voltage - Output
0.125 ~ 1.5 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PWM Controller for IMVP-6+ CPU Core Power Supplies
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
16
PIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
______________________________________________________________________________________
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
(MAX8771)
PHASEGD
(MAX8770
MAX8772)
PGND2
PGND1
NAME
CSP1
BST2
BST1
GND
DH2
DH1
V
DL2
V
DL1
LX2
LX1
CC
DD
Open-Drain, Phase-Good Output. Used to signal the system that one of the two phases either has a fault
condition or is not matched with the other. Detection is done by identifying the need for a large on-time
difference between phases in order to achieve or move towards current balance. PHASEGD is low in
shutdown.
PHASEGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions).
PHASEGD is forced high impedance while in 1-phase operation (DPRSLPVR = high or PSI = low).
Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of
the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing.
Analog Ground. Connect to the exposed backside pad and low-current analog ground terminations.
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.
Boost Flying-Capacitor Connection for the DH2 high-side gate driver. An internal switch between V
BST2 charges the flying capacitor during the time the low-side FET is on.
Phase-2, High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
Phase-2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also
used as an input to the phase 2’s zero-crossing comparator.
Power Ground for Phase 2. Ground connection for the DL2 driver. Also used as an input to phase 2’s zero
crossing comparator.
Phase-2, Low-Side Gate-Driver Output. DL2 swings from PGND2 to V
DL2 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit
condition that may be present. DL2 is forced low in skip mode (DPRSLPVR high) after an inductor current
zero crossing (PGND2 - LX2) is detected. DL2 is forced low in 1-phase mode (TWO - PH = low).
Supply Voltage Input for the DL1 and DL2 Drivers. V
recharge the BST1, BST2 flying capacitors during the off-times of the respective phases. Connect V
the 4.5V to 5.5V system supply voltage. Bypass V
ceramic capacitors.
Phase 1, Low-Side Gate-Driver Output. DL1 swings from PGND1 to V
DL1 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit
condition that may be present. DL1 is forced low in skip mode (DPRSLPVR high) whenever an inductor
current zero crossing (PGND1 - LX1) is detected.
Power Ground for Phase 1. Ground connection for the DL1 driver. Also used as an input to the phase 1’s
zero crossing comparator.
Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also
used as an input to the phase-1’s zero-crossing comparator.
Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between V
and BST1 charges the flying capacitor during the time the low-side FET is on.
FUNCTION
DD
DD
to PGND1 and PGND2 with a 1µF each or greater
is also the supply voltage used to internally
Pin Description (continued)
®
DD
DD
IMVP-6 LICENSEES
. DL1 is forced high in shutdown.
. DL2 is forced high in shutdown.
DD
DD
DD
and
to