DS34T108GN+ Maxim Integrated Products, DS34T108GN+ Datasheet - Page 13

• Manufacturer Part Number: DS34T108GN+
• Description: IC TDM OVER PACKET 484HSBGA
• Manufacturer: Maxim Integrated Products
• Type: TDM (Time Division Multiplexing)r

Specifications of DS34T108GN+

• Applications: Data Transport
• Mounting Type: Surface Mount
• Package / Case: 484-BGA Exposed Pad, 484-eBGA, 484-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6 Pin Descriptions
Table 6-1. Short Pin Descriptions
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
PIN NAME
Internal E1/T1 LIU Line Interface
TXENABLE
TTIPn, TRINGn
RTIPn, RRINGn
RXTSEL
RESREF
External E1/T1 LIU Interface
TCLKOn
TDATFn
RCLKFn / RCLKn
RDATFn
Framer TDM Interface
TCLKFn
TSYSCLKn / ECLKn
TSERn
TSYNCn / TSSYNCn
RSYSCLKn
RSERn
RSYNCn
RFSYNCn/ RMSYNCn
RLOFn/ RLOSn
TDM-over-Packet Engine TDM Interface
TDMn_ACLK
TDMn_TCLK
TDMn_TX
TDMn_TX_SYNC
TDMn_TX_MF_CD
TDMn_TSIG_CTS
TDMn_RCLK
TDMn_RX
TDMn_RX_SYNC
TDMn_RSIG_RTS
SDRAM Interface
SD_CLK
SD_D[31:0]
SD_DQM[3:0]
SD_A[11:0]
SD_BA[1:0]
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
Ethernet PHY Interface (MII/RMII/SSMII)
CLK_MII_TX
CLK_SSMII_TX
MII_TXD[3:0]
MII_TX_EN
MII_TX_ERR
CLK_MII_RX
MII_RXD[3:0]
(1)
TYPE
IOpd
Oa
Ipu
Ipd
Ipu
Ipu
Ipd
Ipu
IO
IO
IO
IO
Ia
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
(2)
PIN DESCRIPTION
LIU Transmit Enable Input (for all LIUs)
LIU Transmitter Analog Outputs
LIU Receiver Analog Inputs
Receive Termination Selection Input (for All LIUs)
Reference Resistor for LIU Analog Circuits (precision 10k to ARVSS)
Transmit Clock Output
Transmit Data Output
Receive Clock Input to Framer (RCLKFn)
or Recovered Clock Output from LIU Receiver (RCLKn)
Receive Data Input to Framer
Transmit Clock Input to Formatter
Transmit System Clock Input (clock for cross-connect side of elastic store)
or External Reference Clock Input
Transmit Serial Data Input
Transmit Frame/Multiframe Sync Input/Output or Transmit System
Frame/Multiframe Sync Input (sync for cross-connect side of elastic store)
Receive System Clock Input (clock for cross-connect side of elastic store)
Receive Serial Data Output
Receive Frame/Multiframe Sync Input/Output
Receive Frame Sync or Receive Multiframe Sync Output
Receive Loss of Frame Output or Receive Loss of Signal Output
TDMoP Recovered Clock Output
TDMoP Transmit Clock Input (here transmit means “toward LIU”)
TDMoP Transmit Data Output
TDMoP Transmit Frame Sync Input
TDMoP Transmit Multiframe Sync Input or Carrier Detect Output
TDMoP Transmit Signaling Output or Clear to Send Output
TDMoP Receive Clock Input (here receive means “toward Ethernet MII”)
TDMoP Receive Data Input
TDMoP Receive Frame/Multiframe Sync Input
TDMoP Receive Signaling Input or Request To Send Input
SDRAM Clock
SDRAM Data Bus
SDRAM Byte Enable Mask
SDRAM Address Bus
SDRAM Bank Select Outputs
SDRAM Chip Select (Active Low)
SDRAM Write Enable (Active Low)
SDRAM Row Address Strobe (Active Low)
SDRAM Column Address Strobe (Active Low)
MII Transmit Clock Input
SSMII Transmit Clock Output
MII Transmit Data Outputs
MII Transmit Enable Output
MII Transmit Error Output
MII Receive Clock Input
MII Receive Data Inputs
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