IDT77V550S25DT8 IDT, Integrated Device Technology Inc, IDT77V550S25DT8 Datasheet - Page 9

• Manufacturer Part Number: IDT77V550S25DT8
• Description: IC SW MEMORY 8X8 1.2BGPS 80-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V550S25DT8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V550S25DT8

Generic ATM Cell to DPI-4 Mapping
Generic ATM Cell to DPI-4 Mapping
Manager Bus Interface
Manager Bus Interface
Switch Manager and the Switch Controller has been defined to require at most four steps (this is a Read Operation):
guarantee that Manager Bus Commands have been completely executed. This is due to the inherent internal activity priority for the State Machine of
the IDT77V500.
traffic was heavy at a particular time. The manager must wait for an acknowledgment from the IDT77V500 before moving on to execute the next
command. Acknowledgment is defined as a HIGH MDATA7 read (MD/C LOW and MR/W HIGH) after loading of the Command (MD/C LOW and
MR/W LOW). It is not necessary to execute a STATUS command to read this Acknowledgment form the Switch Controller. The timing delay from when
the IDT77V550 receives the command cell and when the IDT77V500 acknowledges that the command has been executed can vary greatly. The delay
can be as long as 14 sec during periods of sustained heavy data traffic through the switch, especially when the state machine of the IDT77V500 is
unable to perform the acknowledgment function.
IDT77V500 requires the data registers to be loaded while examining status reads them. The command executed will also determine how many of the
thirteen Data Registers must be written into or read from to complete the operation. Three control signals, MR/W, MD/C, and MSTRB, are used to
access the Switch Controller. MR/W is HIGH to read the controller; LOW to write it. MD/C is LOW to select the command/status register (to issue a
command) and HIGH for the data registers (to Read/Write data into the Controller). During a read operation MSTRB LOW enables the controller to
drive MDATA, effectively acting like an Output Enable pin. On a write command the rising edge of MSTRB clocks MDATA into the IDT77V500. The
IDT77V550
The IDT77V550 Switch Manager communicates with the IDT77V500 Switch Controller over the 8-bit Manager bus. An exchange between the
1. Load the data registers of the IDT77V500. (Address to be read in READ Mode; Data to be written in WRITE Mode.)
2. Write a command to the command register of the IDT77V500.
3. Read the status register of the IDT77V500 until an acknowledgment occurs.
4. Read the requested data registers of the IDT77V500.
The Acknowledgment function, in which the IDT77V500 sets MDATA7 HIGH after a command has been executed, is a necessary procedure to
Since the Manager Bus Commands are the lowest priority in the Switch Controller State Machine, there could be some delays if the actual switch
Which of the four steps required and the meaning of the bits in the data registers depends on the particular command. For example configuring the
DPI Nibble
Count
104
105
10
11
—
—
0
1
2
3
4
5
6
7
8
9
GFC [3:0]
VPI [7:4]
VPI [3:0]
VCI [15:12]
VCI [11:8]
VCI [7:4]
VCI [3:0]
PTI [2:0], CLP
HEC [7:4]
HEC [3:0]
First data byte [7:4]
First data byte [3:0]
Last data byte [7:4]
Last data byte [3:0]
DPI Content
—
—
Table 9 Generic ATM Cell to DPI-4 Mapping
GFC bits for the ATM cell header. First nibble to be transmitted/received.
VPI bits MSB of the ATM cell header.
VPI bits LSB of the ATM cell header.
VCI bits MSB of the ATM cell header.
VCI bits of the ATM cell header.
VCI bits of the ATM cell header.
VCI bits of the ATM cell header.
PTI and CLP bits of the ATM cell header.
HEC Most Significant nibble.
HEC Least Significant nibble.
First data Most Significant nibble of the ATM cell header.
First data Least Significant nibble of the ATM cell header.
Last data byte Most Significant nibble of the ATM cell.
Last data byte Least Significant nibble of the ATM cell.
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Comments
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June 22, 2001