IDT89HPES16T7ZHBXG IDT, Integrated Device Technology Inc, IDT89HPES16T7ZHBXG Datasheet

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IDT89HPES16T7ZHBXG

Manufacturer Part Number
IDT89HPES16T7ZHBXG
Description
IC PCI SW 16LANE 7PORT 320-SBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT89HPES16T7ZHBXG

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89HPES16T7ZHBXG

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Part Number:
IDT89HPES16T7ZHBXG
Manufacturer:
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Quantity:
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Device Overview
Express switching solutions. The PES16T7 is a 16-lane, 7-port periph-
eral chip that performs PCI Express packet switching with a feature set
optimized for high performance applications such as servers, storage
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstream port and up to six down-
stream ports and supports switching between downstream ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES16T7 is a member of the IDT PRECISE™ family of PCI
SerDes
Logical
Layer
Phy
High Performance PCI Express Switch
– Sixteen 2.5 Gbps PCI Express lanes
– Seven switch ports
– Upstream port configurable up to x8
– Two downstream ports configurable up to x4, four downstream
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Multiplexer / Demultiplexer
ports are x1
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
(Port 0)
SerDes
Logical
Layer
Phy
SerDes
Logical
Frame Buffer
Layer
Phy
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
16-Lane 7-Port
PCI Express® Switch
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
7-Port Switch Core / 16 PCI Express Lanes
(Port 1)
SerDes
Logical
Layer
Phy
Route Table
Figure 1 Internal Block Diagram
SerDes
Logical
Layer
Phy
1 of 33
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
(Port 6)
Legacy Support
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Power Management
– PCI compatible INTx emulation
– Bus locking
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
– Utilizes advanced low-power design techniques to achieve low
– Supports PCI Power Management Interface specification (PCI-
– Unused SerDes are disabled
Arbitration
Port
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
server motherboards
typical power consumption
PM 1.1)
• Supports device power management states: D0, D3
SerDes
Logical
D3
Layer
Phy
cold
SerDes
Logical
Layer
Phy
Mux/Demux
Scheduler
(Port 2)
SerDes
Logical
Layer
DLL
Phy
TL
89HPES16T7
Data Sheet
March 25, 2008
Mux/Demux
(Port 5)
SerDes
Logical
Layer
DLL
Phy
TL
hot
and

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IDT89HPES16T7ZHBXG Summary of contents

Page 1

Device Overview The 89HPES16T7 is a member of the IDT PRECISE™ family of PCI Express switching solutions. The PES16T7 is a 16-lane, 7-port periph- eral chip that performs PCI Express packet switching with a feature set optimized for high ...

Page 2

IDT 89HPES16T7 Data Sheet Testability and Debug Features – Ability to read and write any internal register via the SMBus Twelve General Purpose Input/Output pins – Each pin may be individually configured as an input or output – Each pin ...

Page 3

IDT 89HPES16T7 Data Sheet SMBus Interface The PES16T7 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES16T7, allowing every configuration register in the device to be read or written by an external ...

Page 4

IDT 89HPES16T7 Data Sheet Hot-Plug Interface The PES16T7 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES16T7 utilizes an external I/O expander, such as that used on PC motherboards, ...

Page 5

IDT 89HPES16T7 Data Sheet Signal PE6TP[3:0] PE6TN[3:0] PEREFCLKP[2:1] PEREFCLKN[2:1] REFCLKM Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] Type Name/Description O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans- mit pair for port 6. ...

Page 6

IDT 89HPES16T7 Data Sheet Signal GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: ...

Page 7

IDT 89HPES16T7 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE P01MERGEN PERSTN RSTHALT SWMODE[2:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream ...

Page 8

IDT 89HPES16T7 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Type Name/Description O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. ...

Page 9

IDT 89HPES16T7 Data Sheet Signal V CORE APE Type Name/Description I Core VDD. Power supply for core logic. I I/O VDD. LVTTL I/O buffer power supply. ...

Page 10

IDT 89HPES16T7 Data Sheet Pin Characteristics Note: Some input pads of the PES16T7 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

Page 11

IDT 89HPES16T7 Data Sheet Function SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT General Purpose I/O GPIO[11:0] System Pins CCLKDS CCLKUS MSMBSMODE P01MERGEN PERSTN RSTHALT SWMODE[2:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 1. Internal resistor values under typical operating ...

Page 12

IDT 89HPES16T7 Data Sheet Logic Diagram — PES16T7 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 1 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 PCI Express ...

Page 13

IDT 89HPES16T7 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter PEREFCLK Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of ...

Page 14

IDT 89HPES16T7 Data Sheet 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal GPIO 1 GPIO[11:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width ...

Page 15

IDT 89HPES16T7 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express ...

Page 16

IDT 89HPES16T7 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured ...

Page 17

IDT 89HPES16T7 Data Sheet Heat Sink Table 17 lists heat sink requirements for the PES16T7 under two common usage scenarios. As shown in this table, a heat sink is not required in most cases. Air Flow Zero 3.9”x6.2” (ExpressModule form ...

Page 18

IDT 89HPES16T7 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V ...

Page 19

IDT 89HPES16T7 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN ...

Page 20

IDT 89HPES16T7 Data Sheet Package Pinout — 320-BGA Signal Pinout for PES16T7 The following table lists the pin numbers and signal names for the PES16T7 device. Pin Function Alt Pin A1 V B11 B12 ...

Page 21

IDT 89HPES16T7 Data Sheet Pin Function Alt Pin K1 PEREFCLKP1 P22 P23 P24 K21 K22 K23 K24 PEREFCKN2 ...

Page 22

IDT 89HPES16T7 Data Sheet Pin Function Alt Pin AC13 PE0TP03 AC22 AC14 V AC23 SS AC15 V AC24 SS AC16 PE0TP02 AD1 AC17 V AD2 SS AC18 PE0TP01 AD3 AC19 V AD4 SS AC20 PE0TN00 AD5 AC21 V AD6 SS ...

Page 23

IDT 89HPES16T7 Data Sheet Power Pins V Core A16 A18 A19 A21 A23 B20 B22 B23 C2 C21 C24 D1 D3 D20 D22 D23 E4 E24 G1 G24 AA1 AB1 ...

Page 24

IDT 89HPES16T7 Data Sheet Ground Pins A11 A13 A15 A17 A20 A22 A24 B7 B9 B11 B13 B15 B21 B24 H24 C14 ...

Page 25

IDT 89HPES16T7 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE P01MERGEN PE0RN00 PEORN01 PE0RN02 PE0RN03 ...

Page 26

IDT 89HPES16T7 Data Sheet Signal Name PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE1RN00 PE1RN01 PE1RN02 PE1RN03 PE1RP00 PE1RP01 PE1RP02 PE1RP03 PE1TN00 PE1TN01 PE1TN02 PE1TN03 PE1TP00 PE1TP01 PE1TP02 PE1TP03 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PE4RN00 ...

Page 27

IDT 89HPES16T7 Data Sheet Signal Name PE4TP00 PE5RN00 PE5RP00 PE5TN00 PE5TP00 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT ...

Page 28

IDT 89HPES16T7 Data Sheet Signal Name SWMODE_0 SWMODE_1 SWMODE_2 V CORE APE I/O Type Location I W23 I W22 I V24 See Table 21 for a ...

Page 29

IDT 89HPES16T7 Data Sheet PES16T7 Pinout — Top View ...

Page 30

IDT 89HPES16T7 Data Sheet PES16T7 Package Drawing — 320-Pin BX320/BXG320 March 25, 2008 ...

Page 31

IDT 89HPES16T7 Data Sheet PES32T8 Package Drawing — Page Two March 25, 2008 ...

Page 32

IDT 89HPES16T7 Data Sheet Revision History February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Changed device revision in Ordering Information from ZD to ZH. November 14, 2007: Added new ...

Page 33

IDT 89HPES16T7 Data Sheet Ordering Information A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES16T7ZHBX 320-pin BX320 package, Commercial Temperature 89HPES16T7ZHBXG 320-pin Green BX320 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA ...

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