IDT89HPES12NT3ZBBC IDT, Integrated Device Technology Inc, IDT89HPES12NT3ZBBC Datasheet - Page 6

• Manufacturer Part Number: IDT89HPES12NT3ZBBC
• Description: IC PCI SW 12LANE 3PORT 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES12NT3ZBBC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES12NT3ZBBC

IDT 89HPES12NT3 Data Sheet
MSMBSMODE
SWMODE[3:0]
PENTBRSTN
JTAG_TCK
JTAG_TDI
RSTHALT
Signal
CCLKDS
CCLKUS
PERSTN
Signal
Type
Type
I
I
I
I
I
I
I
I
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstream device
and the downstream port.
Common Clock Upstream. When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstream device and
the upstream port.
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Non-Transparent Bridge Reset. Assertion of this signal indicates a reset
on the external side of the non-transparent bridge. This signal is only used
when the switch mode selects a non-transparent mode and has no effect
otherwise.
Fundamental Reset. Assertion of this signal resets all logic inside the
PES12NT3 and initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES12NT3 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES12NT3 switch
operating mode.
0x0 - Reserved
0x1 - Reserved
0x2 - Non-transparent mode
0x3 - Non-transparent mode with serial EEPROM initialization
0x4 - Non-transparent failover mode
0x5 - Non-transparent failover mode with serial EEPROM initialization
0x6 through 0xF - Reserved
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 5 Test Pins (Part 1 of 2)
Table 4 System Pins
6 of 29
Name/Description
Name/Description
February 19, 2009