IDT77V400S156BCG IDT, Integrated Device Technology Inc, IDT77V400S156BCG Datasheet - Page 7

• Manufacturer Part Number: IDT77V400S156BCG
• Description: IC SW MEMORY 8X8 1.2BGPS 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156BCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 77V400S156BCG

Pin Description - BGA Package
Pin Description - BGA Package
Pin Description - BGA Package
Pin Description - BGA Package
94
206
207
1, 52-54, 104-06,
156-59
2, 15-16, 41-42, 49-
50, 56, 67-68, 83-84,
101-02, 108, 119-20,
126, 140, 154, 165,
184, 193, 204
55, 107, 208
3-4, 28-29, 43-44,
51, 61-62, 73, 82, 85,
96, 103, 113-14,
125, 127, 141, 155,
164, 183, 194, 203
J14
F14
G14-16, H14-16
P13
A14
J15-16, K14, K16
B1, C1-3, D1-3,E1-3,
F1-3, G1-3, H1-3,
J1-3, K1-3, L1-3, M1-
3, N3
A2
Pin Number
Pin Number
IDT77V400
CTLEN
NC
VCC
VCCQ
VSS
SCLK
CS
OE
RESET
ADDR0-3
IOD0-31
CRCERR
ABYTE
SBYTE
CMD0-5
Symbol
Symbol
I
I
I
—
Power
Power
Power
I
I
I
I
I
I
I/O
O
Type
Type
Control Enable: When asserted LOW, with OE LOW and the CTLEN bit set LOW in the configuration register, this pin
asynchronously enables all Control interface outputs. If CTLEN is HIGH all control interface outputs will be High-Z.
Add Byte to Input cell: Asynchronous DC signal. If an input port is in a 4-bit or 8-bit DPI mode and ABYTE is asserted
HIGH, a dummy byte will be inserted in the ninth byte position (after the HEC byte) to support systems requiring a byte
between the last header byte and the payload (otherwise ignored). Not intended for dynamic cycling or operation.
Subtract Byte to Output cell: Asynchronous DC signal. When and SBYTE is asserted HIGH, the dummy byte in the
ninth byte position (after the HEC byte) will be removed prior to transmission to support output port 4-bit and 8-bit DPI
modes (otherwise ignored). Not intended for dynamic cycling or operation.
No Connect
Power Supply (+3.3V ± 300mV)
Output Power Supply (+3.3 ± 300mV)
Ground
System clock: All bus control signals (CMD0-5, CS, IOD0-31, CRCERR) except OE are synchronous with respect to
SCLK. Control commands are registered on the positive edge of SCLK. The SCLK period must be less than or equal to
200ns during normal operation. Data Port signals are asynchronous with respect to SCLK.
Chip Select: Synchronous input which must be LOW at the rising edge of SCLK to enable the Command Bus CMD0-5.
Instructions are a NOP when CS is HIGH at the SCLK positive edge.
Command Bus: Synchronized to SCLK, instructions to be executed by the memory are transferred across this 6-bit
bus. CMD5 is the MSb of the Command Bus.
Output Enable: Asynchronous input that enables all outputs when asserted LOW. All outputs are High-Z when OE is
HIGH. IOD0-31 and CRCERR may also be set to High-Z by a HIGH CTLEN bit in the configuration register or a HIGH
CTLEN pin.
Reset: When asserted HIGH, the signal asynchronously allows the initialization of the registers and internal signals of
the IDT77V400. RESET should be asserted HIGH and OE should be held HIGH upon power-up for the external con-
troller to execute the initialization and insure proper system operation.
Chip Address: All ADDR inputs must OR the address in the configuration register bits 26-29 and then must match
1OD13-16 one cycle after the Store or Load command for selection to allow a Store or Load memory cycle to be exe-
cuted (full flag is cleared regardless of match, and empty must match before clear). ADDR3 is the MSb of the device
address bits.
Control Data Bus: Synchronous with SCLK. Used for external data transfer for the header pre/post-pend bytes, config-
uration register error and status registers, and the cell memory address. IOD31 is the MSb of the Control Data Bus.
Cyclical Redundancy Check Error: Synchronous output on the rising edge of SCLK.CRCERR asserted LOW after a
Header with CRC operation indicates that a CRC error has occurred on the previous header.
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Description
Description
March 31, 2001