IDT72V51336L7-5BB IDT, Integrated Device Technology Inc, IDT72V51336L7-5BB Datasheet - Page 47

• Manufacturer Part Number: IDT72V51336L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51336L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51336L7-5BB

Cycle:
*A*
*AA* Queue 3 of Device 5 is selected for read operations.
*B*
*BB* Word, Wa+1 is read from Qx of D5, due to FWFT operation.
*C*
*CC* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.
*D*
*DD* The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and are placed onto the outputs. The previously selected device now places its
*E*
*EE* Word, Wy+2 is read from Q3 of D5.
*F*
*FF* The PAEn bus updates to show that Q3 of D5 is almost empty based on the reading out of word, Wy+1.
IDT72V51336/72V51346/72V51356 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Device 5 PAEn
Device 5 PAE
Queue 3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
Another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
Word Wp+1 is written into the previously selected queue.
Word, Wn is written into the newly selected queue, Q3 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
t
Device 5 is selected on the PAEn bus. Q3 of device 5 will therefore have is PAE status output on PAE[3]. There is a single RCLK cycle latency before the PAEn bus changes
to the new selection.
Queue 2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of D5.
PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q3 of D5.
The discrete PAE flag will go HIGH to show that Q3 of D5 is not almost empty. Q3 of device 5 will have its PAE status output on PAE[3].
No writes occur.
Device 4 is selected on the write port for the PAFn bus.
Word, Wx is written into Q2 of D3.
The discrete PAE flag goes LOW to show that Q3 of D5 is almost empty based on the reading of Wy+1.
Device 5 -Qn
SKEW3
Prev PAEn
Bus PAEn
WADEN
WRADD
RDADD
RADEN
+ RCLK + t
FSTR
WCLK
ESTR
RCLK
REN
WEN
Dn
RAE
D5 Qx
Wa
(if t
t
t
QS
ENS
SKEW3
t
AS
t
QS
1000011
D5Q3
Previous value loaded on to PAE bus
D5 Qx Status
Previous value loaded on to PAE bus
is violated one extra RCLK cycle will be added.
t
Wp
AS
*A*
Writes to Previous Q
1000011
Figure 26. PAE
D5Q3
*AA*
t
t
AH
QH
t
AH
t
t
DS
QH
PAE
PAE n - Direct Mode, Flag Operation – Devices in Expansion
PAE
PAE
Wp+1
*B*
1
*BB*
t
DH
t
A
t
t
DS
STS
t
AS
D5 Q3
*C*
Wn
2
101xxxx
Device 5
Wa+1
D5 Qn
*CC*
t
DH
t
SKEW3
47
1
t
t
A
QS
t
AS
t
t
t
AH
RAE
STH
t
0110010
ENS
Wn+1
D5Q3
D3Q2
D5 Q3
status
t
PAEZL
*D*
Wy
D5 Q3
*DD*
t
t
AH
t
2
QH
t
ENH
A
t
t
RAE
PAEHZ
*E*
Wy+1
D5 Q3
*EE*
t
STS
t
t
ENS
A
t
Device 5
Device 5
xxx1xxx
AS
xxx1xxx
100xxxx
COMMERCIAL AND INDUSTRIAL
Device 4
D3 Q2
*F*
Wx
Wy+2
D5 Q3
*FF*
t
AH
TEMPERATURE RANGES
t
t
STH
ENH
t
A
t
PAE
t
ENH
t
RAE
Device 5
Device 5
xxx1xxx
xxx1xxx
Wy+3
D5 Q3
5936 drw29