IDT72T6480L10BB IDT, Integrated Device Technology Inc, IDT72T6480L10BB Datasheet - Page 23

• Manufacturer Part Number: IDT72T6480L10BB
• Description: IC FLOW-CTRL 48BIT 10NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6480L10BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6480L10BB

SIGNAL DESCRIPTIONS
INPUTS
DATA INPUTS (D
(D
CONTROLS
MASTER RESET (MRS)
then HIGH. This operation sets the internal read and write pointers to the first
location of the RAM array. PAE will go LOW, PAF will go HIGH.
with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT
is HIGH, then the First Word Fall Through mode (FWFT), along with IR and
OR, are selected. OR will go HIGH and IR will go LOW.
of MRS.
Reset is required after power up, before a write operation can take place. MRS
is an asynchronous function.
PARTIAL RESET (PRS)
HIGH. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, and PAF goes
HIGH.
First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then OR will go HIGH, and IR will go LOW.
unchanged. The output register is initialized to all zeroes. PRS is asynchronous.
when reprogramming programmable flag offset settings may not be convenient.
ASYNCHRONOUS WRITE (ASYW)
mode of operation. If during Master Reset the ASYW input is LOW, then
asynchronous operation of the write port will be selected. During asynchronous
operation of the write port the WCLK input becomes WR input, this is the
asynchronous write strobe input. A rising edge on WR will write data present
on the data inputs into the sequential flow-control device (SFC). (WEN must be
LOW when using the write port in asynchronous mode).
be operating on IDT standard mode, FWFT mode is not permissable. The full
flag (FF) and programmable almost full flag (PAF) operates in an asynchronous
manner, that is, the full flag and PAF flag will be updated based in both a write
operation and read operation. Note, if asynchronous mode is selected, FWFT
is not permissible. Refer to Figure 24, Asynchronous Write and PAE flag – IDT
Standard mode and Figure 25, Asynchronous Write and PAF flag – IDT
Standard mode for relevant timing and operational waveforms.
ASYNCHRONOUS READ (ASYR)
mode of operation. If during a Master Reset the ASYR input is LOW, then
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
0
Data inputs for 48-bit wide data (D
A Master Reset is accomplished whenever the MRS input is toggled LOW
All configuration control signals must be set prior to the LOW to HIGH transition
During a Master Reset, the output register is initialized to all zeroes. A Master
See Figure 6, Master Reset and Initialization, for the relevant timing diagram.
A Partial Reset is accomplished whenever the PRS input is toggled LOW then
Whichever mode is active at the time of Partial Reset, IDT Standard mode or
Following Partial Reset, all values held in the offset registers remain
A Partial Reset is useful for resetting the device during the course of operation,
See Figure 7, Partial Reset, for the relevant timing diagram.
The write port can be configured for either synchronous or asynchronous
When the write port is configured for asynchronous operation the device must
The read port can be configured for either synchronous or asynchronous
If FWFT is LOW during Master Reset then the IDT Standard mode, along
- D
23
) or data inputs for 12-bit wide data (D
0
- D
47
)
0
- D
47
), data inputs for 24-bit wide data
0
- D
11
).
23
asynchronous operation of the read port will be selected. During asynchronous
operation of the read port the RCLK input becomes RD input, this is the
asynchronous read strobe input. A rising edge on RD will read data from the
SFC via the output register and data output port. (REN must be tied LOW during
asynchronous operation of the read port).
asynchronous manner.
be operating on IDT standard mode, FWFT mode is not permissible if the read
port is asynchronous. The Empty Flag (EF) and programmable almost empty
flag (PAF) operates in an asynchronous manner, that is, the empty flag and PAE
will be updated based on both a read operation and a write operation. Refer
to Figure 23, Asynchronous Read and PAF flag – IDT Standard mode, Figure
26, Asynchronous Empty Boundary – IDT Standard mode, Figure 27,
Asynchronous Full Boundary – IDT Standard mode,, and Figure 28, Asyn-
chronous Read and PAE flag – IDT Standard mode, for relevant timing and
operational waveforms.
FIRST WORD FALL THROUGH (FWFT)
device will operate in IDT standard mode or First Word Fall Through (FWFT)
mode.
be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the SFC. It also uses the Full Flag function (FF)
to indicate whether or not the SFC has any free space for writing. In IDT
Standard mode, every word read from the SFC, including the first, must be
requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Q
whether or not the SFC has any free space for writing. In the FWFT mode, the
first word written to an empty SFC goes directly to Q
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
WRITE STROBE AND WRITE CLOCK (WR/WCLK)
input behaves as WCLK.
hold times must be met with respect to the LOW-to-HIGH transition of the WCLK.
It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/IR, and
PAF flags will not be updated. The Write and Read Clocks can either be
independent or coincident.
Data is asynchronously written into the SFC via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be LOW.
WRITE ENABLE (WEN)
edge of every WCLK cycle if the device is not full. Data is stored in the RAM
array sequentially and independently of any ongoing read operation.
further write operations. Upon the completion of a valid read cycle, FF will go
HIGH allowing a write to occur. The FF is updated by two WCLK cycles + t
after the RCLK cycle.
The OE input provides three-state control of the Qn output bus, in an
When the read port is configured for asynchronous operation the device must
During Master Reset, the state of the FWFT input determines whether the
If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
If synchronous operation of the write port has been selected via ASYW, this
A write cycle is initiated on the rising edge of the WCLK input. Data setup and
If asynchronous operation has been selected this input is WR (write strobe).
When the WEN input is LOW, data may be loaded into the SFC on the rising
When WEN is HIGH, no new data is written in the SFC.
To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting
n)
. It also uses Input Ready (IR) to indicate
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
n
after three RCLK rising
SKEW