IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 18

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

Configuration Register Definition
Configuration Register Definition
Configuration Register Definition
Configuration Register Definition
CMD0-5
IOD BUS
CMD0-5
IOD0-31
IOD BUS
1
2
IOD0-31
1
2
3
IDT77V400
MODE
CS is Low.
The 13-bit cell address and 4-bit selected Switching Memory address and 5-bits Edit Buffer Protect and Clear control bits are valid at this time.
MODE
CS is Low.
The 13-bit cell address and 4-bit selected Switching Memory address and 5-bit Edit Buffer Protect and Clear control bits are valid at this time.
The 13-bit cell address and 4-bit selected Switching Memory address are valid at this time; Clear control bits are ignored during the Load sequence.
SCLK
SCLK
0-3
4-7
8-10
11-16
17-19
20-25
26-29
30
31
Register Bits
1.
2.
Configuration Register Bit number corresponds to the same bit position on the IOD bus. Bit 0 is the LSb bit; bit 31 is the MSb.
This bit is not stored in the Configuration Register. It must be asserted on the IOD bus to generate asynchronous reset operation.
REFRESH
OSAM
LOAD
Input
Input
OR HEADER
Address
STATUS
Cell
GET
1
Figure 12 Multi - Sequence Functional Waveform Example - Refresh, Memory Store, Initiate Load
Figure 11 Multi-Sequence Functional Waveform Example - Load, Memory Store, Initiate Refresh
ISAM Configuration
OSAM Configuration
ISAM Start
ISAM Stop
OSAM Start
OSAM Stop
Chip Address
Reset
CTLEN
Input
Output
2
Header
Field Name
Status
Data
Port
STATUS
STATUS
GET
GET
REFRESH SEQUENCE
LOAD SEQUENCE
Output
Output
GET ISAM HEADER
GET ISAM HEADER
Status
Port
Status
Port
Output
Output
Four bit configuration code for the input ports as defined in the Table of configuration codes.
Four bit configuration code for the output ports as defined in the Table of configuration codes.
Three bit starting byte position for the ISAMs.
Six bit stop byte position for the ISAMs.
Three starting byte position for the OSAMs.
Six bit stop byte position for the OSAMs.
Four bit field for multiple device configurations.
One bit used to reset the status and output waiting bits.
One bit used for the Control Interface outputs during parallel operation.
REFRESH CYCLE
LOAD CYCLE
Header
Header
Old
STORE
STORE
Old
ISAM
ISAM
18 of 26
Input
Input
PUT HEADER
Address
PUT HEADER
Address
Cell
Cell
2
2
Input
Input
MEMORY STORE SEQUENCE
MEMORY STORE SEQUENCE
Header
Header
Field Description
New
New
STATUS
STATUS
GET
GET
Output
Output
Status
Status
Port
Port
STATUS
STATUS
GET
GET
Output
Output
MEMORY STORE CYCLE
MEMORY STORE CYCLE
Status
Status
Port
Port
REFRESH
LOAD
OSAM
1
1
Input
Input
Address
Cell
March 31, 2001
OR HEADER
STATUS
GET
3
SEQUENCE
Input
Output
SEQUENCE
REFRESH
LOAD
3606 drw 17
Header
Data
3606 drw 18
Status
Port