IDT72P51749L6BB IDT, Integrated Device Technology Inc, IDT72P51749L6BB Datasheet - Page 4

• Manufacturer Part Number: IDT72P51749L6BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51749L6BB

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 3.7ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51749L6BB

Figure 55. Reading in Packet Mode during a Queue change ......................................................................................................................................... 70
Figure 56. Writing Demarcation Bits (Packet Mode) ........................................................................................................................................................ 71
Figure 57. Data Output (Receive) Packet Mode of Operation ......................................................................................................................................... 72
Figure 58. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 73
Figure 59. Almost Full Flag Timing ................................................................................................................................................................................. 73
Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode) ......................................................................................................................... 74
Figure 61. Almost Empty Flag Timing ............................................................................................................................................................................. 74
Figure 62. PAEn/PRn - Direct Mode - Status Word Selection ......................................................................................................................................... 75
Figure 63. PAFn - Direct Mode - Status Word Selection ................................................................................................................................................. 75
Figure 64. PAEn - Direct Mode, Flag Operation ............................................................................................................................................................. 76
Figure 65. PAFn - Direct Mode, Flag Operation ............................................................................................................................................................. 77
Figure 66. PAFn Bus - Polled Mode .............................................................................................................................................................................. 78
Figure 67. Expansion using ID codes ............................................................................................................................................................................ 79
Figure 68. Expansion using WCS/RCS ......................................................................................................................................................................... 80
Figure 69. Expansion Connection Read Chip Select (RCS) ........................................................................................................................................... 81
Figure 70. Expansion Connection Write Chip Select (WCS) ........................................................................................................................................... 81
Figure 71. Boundary Scan Architecture ......................................................................................................................................................................... 82
Figure 72. TAP Controller State Diagram ....................................................................................................................................................................... 83
Figure 73. Standard JTAG Timing .................................................................................................................................................................................. 86
IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits
List of Figures (Continued)
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SEPTEMBER 27, 2004