IDT88P8341BHGI IDT, Integrated Device Technology Inc, IDT88P8341BHGI Datasheet - Page 9

• Manufacturer Part Number: IDT88P8341BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8341BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8341BHGI

2. PIN DESCRIPTION
SPI-3
SPI-3 is in Link mode or in PHY mode. The SPI-3 interface is configurable for
either Link or PHY mode. This configuration pertains to both the ingress and
egress paths. The device pin is given a generic name, and mapped to the
standard pin name according to the mode of the interface (Link or PHY).
TABLE 1 – I/O TYPES
TABLE 2 – SPI-3 INGRESS INTERFACE PIN DEFINITION
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
Generic Name
For the SPI-3 interface, each pin is used differently depending whether the
I_FCLK
RVAL
I_ENB
I_DAT[31:0]
I_MOD[1:0]
I_PRTY
I_SOP
I_EOP
I_ERR
I_SX
I/O type
I_ST
I-PU
B-PU
I_PD
I
O
O-Z
OD
Input with weak pull up
SPI3A_I_FCLK
Input with Schmitt trigger with weak pull up
Bidirectional I/O with weak pull up
Input with pull down
Input
Output
Output with tri-state
Output with open drain
SPI3A_I_RVAL
SPI3A_I_ENB
SPI3A_I_DAT[31:0]
SPI3A_I_MOD[1:0]
SPI3A_I_PRTY
SPI3A_I_SOP
SPI3A_I_EOP
SPI3A_I_ERR
SPI3A_I_SX
Specific Name
Function
I/O type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
B-PU
B-PU
I-PU
I-PU
I-PU
I-PU
I-PU
I-PU
I-PU
I-ST
Ingress SPI-3 write clock
Receive data valid
Ingress read enable
Ingress data bus
Ingress word modulus
Ingress parity
Ingress start of packet
Ingress end of packet
Ingress EOP error
Ingress start of transfer
Description
9
RFCLK
RVAL (I)
RENB (O)
RMOD [1:0]
RPRTY
RSOP
REOP
RERR
RSX
RDAT [31:0]
Link
Mode
TFCLK
RVAL (O)
TENB (I)
TDAT [31:0]
TMOD [1:0]
TPRTY
TSOP
TEOP
TERR
TSX
PHY
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006