IDT72T55258L5BB IDT, Integrated Device Technology Inc, IDT72T55258L5BB Datasheet - Page 28

• Manufacturer Part Number: IDT72T55258L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55258L5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55258L5BB

SELECTABLE MODES
and Broadcast Write. Each of these three modes can be selected based on the
MD[1:0] bits. These bits should be tied directly to V
in during master reset. The state of the MD pins for each mode is summarized
in Table 1 – Device Configuration.
having densities of 327,680 bits for the IDT72T55248, 655,360 bits for the
IDT72T55258 and 1,310,072 bits for the IDT72T55268. The density of each
Queue is fixed and cannot be programmed. Also, the density does not change
when the device is operating in single or double data rate, or when the device
is utilizing the bus-matching feature.
associated with converging multiple data rates onto one path. Such issues
include clock skew, race conditions, and meeting setup and hold times. These
issues are difficult to address when performing mux operations from external
logic or within an FPGA, especially at higher frequencies. The complexity of the
design makes it difficult to implement within an FPGA, where speed degradations
occur as the circuit becomes more complicated.
MUX MODE
diagram on page 1. The device in this mode consists of four separate Queues:
Queue 0, Queue 1, Queue 2 and Queue 3. The four Queues all have the same
common read port, and the read control selecting which Queue to read from.
The Mux mode can be used in applications where multiple incoming data rates
from different data paths are being buffered to one common data rate and data bus.
WRITE PORT OPERATION
Queue. Data can be written to any of the four Queues using its corresponding
write clock, write enable, and write chip select. A data word will be written on
the rising (and falling in DDR) edge of write clock provided WEN and write chip
select are active. Note in double data rate the setup and hold times of the write
enables and write chip selects are sampled with respect to the rising edge of its
respective write clock only. The falling edge of WCLK does not sample the write
enable and write chip select.
onto the output bus of that respective Queue when selected on the read port via
the OS[1:0] pins. There is a two cycle input pipeline and a two cycle output
pipeline. It will take two cycles or three rising edges of the WCLK to move data
from the write port to the queue and two cycles or those rising edges of RCLK
to move data from the queue to the data outlines. This is regardless of the state
of the corresponding read enable and read chip select, provided that the
selected Queue was empty. This is not true in IDT Standard mode, where the
first word written to a selected Queue must be accessed by setting REN and RCS
are LOW on the rising edge of RCLK.
READ PORT OPERATION
Queues the output bus will read data from. The output select pins are sampled
on the rising edge of every RCLK, and may change on every clock edge. Thus
there is no latency switching from one Queue to another. Note that in Mux mode
only the RCLK0 is active, all other output read clocks are not used. The same
applies to the read enable (REN0) and read chip select (RCS0). Data will be
read on the rising (and falling in DDR) edge of read clock provided read enable
and read chip select are active (LOW). When selecting a Queue for read
operations the new word read from that Queue will be available immediately on
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The device is capable of operating in three different modes, Mux, Demux,
Each mode has access to four dedicated Queues internally, with each Queue
The QuadMux flow-control device accommodates for all of the timing issues
In Mux mode the device is configured as shown in the Mux mode block
In Mux mode there are four independent write port controls for each individual
In FWFT mode the first word written to any Queue will automatically be placed
In Mux mode the output select pins (OS[1:0]) determine which one of the four
CC
or GND as they are latched
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the next clock edge after the new Queue is selected. For example, if OS[1:0]
is set to 01 (Queue1) on RCLK edge 0, then on RCLK edge 1 (next read clock
edge) data can be read from Queue1 if REN0 and RCS0 are enabled.
be placed onto the output bus of that respective Queue regardless of the state
of the corresponding read enable, provided that the selected Queue was empty
and its corresponding output ready flag was inactive. This occurs due to the
nature of the FWFT flag timing. There is a two cycle input pipeline and a two cycle
output pipeline. It will take two cycles or three rising edges of the WCLK to move
data from the write port to the queue and two cycles or those rising edges of RCLK
to move data from the queue to the data outlines. Subsequent writes to the Queue
that is not empty will not fall through to the output bus. Note in FWFT mode, during
a Queue selection the next word available in the Queue will automatically fall
through to the output bus regardless of the read enable and read chip select.
by the read enable and read chip select. Unlike FWFT mode, during a Queue
selection the next word available in the Queue will not automatically fall through
to the output bus. The previous word that was read out of the read port will remain
on the output bus if the REN and RCS select are HIGH.
DEMUX MODE
diagram on page 2. The device in this mode consists of four separate Queues:
Queue 0, Queue 1, Queue 2 and Queue 3. The four Queues all have the same
common write port, and the read control selecting which Queue to read from.
The Demux mode can be used in applications where a single incoming data
rate is being buffered to multiple outgoing data rates.
WRITE PORT OPERATION
Queues the input bus will write data into. The input select pins are sampled on
the rising edge of every WCLK, and may change on every clock edge. Thus
there is no latency switching from one Queue to another. Note that in Demux
mode only the WCLK0 is active, all other input write clocks are not used. The
same applies to the write enable (WEN0) and write chip select (WCS0). Data
will be written on the rising (and falling in DDR) edge of write clock provided WEN
and WCS are active on the rising edge of the WCLK. Note in double data rate
the setup and hold times of the WEN and WCS selects are sampled with respect
to the rising edge of the write clock only. The falling edge of WCLK does not
sample the write enable and write chip select. When selecting a Queue for write
operations the next word can be written to that Queue immediately on the next
clock edge after the new Queue is selected. For example, if IS[1:0] is set to 01
(Queue1) on WCLK edge 0, then on WCLK edge 1 (next read clock edge) data
can be written to Queue1 if WEN0 and WCS0 are enabled.
be placed onto the output bus regardless of the state of the corresponding read
enable, provided that the selected Queue was empty and its corresponding
output ready flag was inactive. There is a two cycle input pipeline and a two cycle
output pipeline. It will take two cycles or three rising edges of the WCLK to move
data from the write port to the queue and two cycles or those rising edges of RCLK
to move data from the queue to the data outlines. This occurs due to the nature
of the FWFT flag timing. Subsequent writes to the Queue that is not empty will
not fall through to the output bus. In IDT Standard mode, every word including
the first word must be accessed by the read enable and read chip select.
READ PORT OPERATION
individual Queue. Data can be read from any of the four Queues using its
In FWFT mode, the first word written to a selected Queue will automatically
In IDT Standard mode, every word including the first word must be accessed
In Demux mode the device is configured as shown in the Demux mode block
In Demux mode the input select pins (IS[1:0]) determine which one of the four
In FWFT mode the first word written to a selected Queue will automatically
In Demux mode there are four independent read port controls for each
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009