IDT72T55258L6-7BBI IDT, Integrated Device Technology Inc, IDT72T55258L6-7BBI Datasheet - Page 6

• Manufacturer Part Number: IDT72T55258L6-7BBI
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55258L6-7BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55258L6-7BBI

DESCRIPTION
are ideal for many applications where data stream convergence and parallel
buffering of multiple data paths are required. These applications may include
communication and networking systems such as terabit routers, quality of
service (QOS) and packet prioritization routing systems, data bandwidth
aggregation, data acquisition systems, WCDMA baseband systems, and
medical equipments. The QuadMux replaces traditional methods of muxing
multiple data paths at different data rates, in essence reducing external glue
logic. The QuadMux offers three modes of operation, Mux, Demux and
Broadcast. Regardless of the mode of operation there are four internal
Sequential Queues built using IDT FIFO technology and five discrete clock
domains. All four Queues have the same density, and the read and write ports
can operate independently in Single Data Rate (SDR) or Double Data Rate
(DDR). See Figure 1, QuadMux Block Diagram or an outline of the functional
blocks within the device.
SDR or DDR data transfer modes for the inputs and outputs. In SDR mode,
the input clock can operate up to 200MHz. Data will transition/latch on the rising
edge of the clock. In DDR mode, the input clock can operate up to 100 MHz,
with data transitioning/latched on both rising and falling edges of the clock. The
advantage of DDR is that it can achieve the same throughput as SDR with only
half the number of bits, assuming the frequency is constant. For example, a
4Gbps throughput in SDR is 100MHz x 40 bits. In DDR mode, it is 100MHz x
20 bits, because two bits transition per clock cycle.
output port). Here there are four internal Sequential Queues each with a
dedicated write port. Data can be written into each of the dedicated write ports
totally independent of any other port, each port has its own write clock input and
control enables. There is a single read port that can access any one of the four
Queues. Data is read out of a specific Queue based on the address present
on the output select pins. Only one Queue can be selected and read from at
a time. All input ports are 10 bits wide and the output port has a selectable Bus
Matching x10, x20 or x40 bus widths. A full set of flag outputs per Queue are
available in this mode providing the user with continuous status of each
individual Queue levels.
output ports). Here there is a single write port that can write data into any one
of four internal Queues. Data is written into a specific Queue based on the
address present on the input select pins. Only one Queue can be selected and
written into at a time. There are four dedicated read ports, one port for each
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The IDT72T55248/72T55258/72T55268 QuadMux flow-control devices
The QuadMux device offers a maximum throughput of 8Gbps, with selectable
In Mux mode operation a 4:1 architecture is setup, (four input ports to one
In Demux mode operation a 1:4 architecture is setup, (one input port to four
6
Queue. Data can be read out of the four Queues through the read port totally
independent of any other port. Each port has its own read clock input and control
enables. The input port has a selectable Bus Matching x10, x20 or x40 bus width
and all the output ports are 10-bits. A full set of flag outputs per Queue are
available in this mode providing the user with continuous status of each individual
Queue levels.
1:4 (one input port to four output ports). However, there is no Queue select
operation in Broadcast mode. Instead data written into the write port is written
to all four internal Queues simultaneously. Again there are four independent
read ports, one port per Queue. In Broadcast mode write operations to all
Queues will be prevented when any one or more of the four Queues are full
or being partially reset. A full set of flag outputs is available in this mode providing
the user with continuous status of each individual Queue levels.
available, IDT Standard mode and First Word Fall Through (FWFT) mode. This
affects the device’s operation and also the flag outputs. The device provides four
flag outputs, for each internal Queue. The device also provides composite flags
that represent the full and empty status of the currently selected Queue.
and an Echo Read Clock, ERCLK output. These outputs aid in high-speed
applications where synchronization of the input clock and data of a receiving
device is critical. Otherwise known as “Source Synchronous clocking” the echo
outputs provide tighter synchronization of the data transmitted from the Queue
to the read clock interfacing the Queue outputs.
latched with respect to a Master Reset. A Partial Reset is provided for each
internal Queue. When a Partial Reset is performed on a Queue the read and
write pointers of that Queue only are reset to the first memory location. The flag
offset values, timing modes, and initial configurations are retained.
LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, V
is provided for HSTL and eHSTL interfaces. The type of I/O is selected by the
IOSEL pin. There are certain inputs that are CMOS based and must be tied to
either V
however the output pins have a separate supply, V
or 1.5V. The device also offers significant power savings, achieved through the
use of the Power Down input, PD in HSTL/eHSTL mode.
is fully compliant with IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture. The JTAG port can also be used to program the flag offsets.
In the Broadcast Write mode the architecture is similar to the Demux mode,
As is typical with most IDT Queues, two types of data timing modes are
All read ports provide the user with a dedicated Echo Read Enable, EREN
A master reset input is provided and all setup and configuration pins are
The QuadMux device has the capability of operating its I/Os at either 2.5V
A JTAG test port is provided on the QuadMux device. The Boundary Scan
CC
or GND. The core supply voltage of the device, V
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DDQ
FEBRUARY 01, 2009
which can be 2.5V, 1.8V
CC
is always 2.5V,
REF
input