IDT77V500S25PF IDT, Integrated Device Technology Inc, IDT77V500S25PF Datasheet - Page 9

• Manufacturer Part Number: IDT77V500S25PF
• Description: IC SW MEMORY 8X8 1.2BGPS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V500S25PF

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V500S25PF

Control Interface Timing Waveform
Control Interface Timing Waveform
Control Interface Timing Waveform
Control Interface Timing Waveform
Control Interface Commands
Control Interface Commands
Control Interface Commands
Control Interface Commands
SFRM, CBUS, and OFRM Timing Waveforms
SFRM, CBUS, and OFRM Timing Waveforms
SFRM, CBUS, and OFRM Timing Waveforms
SFRM, CBUS, and OFRM Timing Waveforms
GHIx
GST
GER
STEx
LDOx
PHE
PHEC
REF
LDC
OHE
OHEC
1
1
IDT77V500
1.
2.
3.
The result of this GET STATUS command is that an ISAM is full and ready to be stored to the Cell Memory of the IDT77V400.
OFRM1-7 become CBUS1-7 (Outputs) during cell bus operations to arbitrate between multiple IDT77V500's.
Command
This waveform describes the command interaction across the IOD Bus to the IDT77V400 Switching Memory.
CMD bus commands not defined in this table are undefined and are not implemented by the IDT77V500.
"x" represents the specific ISAM or OSAM being accessed (IP0-IP7 or OP0-OP7 respectively).
"n" represents the appropriate bit of the binary representation of the ISAM or OSAM being accessed (000 to 111).
CRCERR
IOD0-31
SCLK
CMD0-5
OFRM/CBUS
1
OFRM
SFRM
SCLK
Get Header from ISAMx
Get ISAM Status Register Bits
Get Error Register Bits
Store Cell in ISAMx
Load Cell from Memory into OSAMx
Put new Header in Edit Buffer
Put new Header and new CRC byte in Edit Buffer
Refresh Cell Memory
Load Configuration Register
Put new Header in Output Edit Register
Put new Header and new CRC byte in Output Edit Register
1
STATUS
GET
1
t
CH
t
CYC
2
t
Command Description
CL
and Edit Buffer in Memory
STATUS
STATUS
GET
2
t
CDC
1
HEADER ISAM
2
STATUS
t
OFP
GET
(1)
(1)
(1)
(1)
t
DCC
t
SIO
Old Header
Input -
STORE
ISAM
9 of 17
t
t
CDIO
HIO
t
t
SCRC
CDOF
t
HEADER
CDS
Cell Addr
[ CRC ERROR = LOW ]
Output -
PUT
t
DCIO
t
HCRC
t
CDIO
MSb
5
0
0
0
1
1
1
1
0
1
1
1
t
DCOF
t
DCS
New Header
Output -
[ AVAILABLE FOR NEXT COMMAND ]
t
DCIO
4
0
1
1
0
1
1
1
1
1
1
1
Command Bus Bit (CMD5:0)
3
1
0
0
0
0
1
1
0
1
1
1
2
n
0
1
n
n
1
1
1
0
1
0
3
3
3
3607 drw 07
3607 drw 06
1
n
1
1
n
n
0
0
1
1
1
0
3
3
3
April 11, 2001
LSb
0
n
0
0
n
n
0
1
1
0
0
1
3
3
3