DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 93

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Considerations
Select the HDLC Controller connection. The default setting connects it to the DS3/E3 Framers.
PORT.CR1.HDSEL = 1 connects the HDLC Controller to the PLCP framers.
In POS-PHY mode, to select cell processing rather than packet processing, set PORT.CR2.PMCPE = 1.
9.1 Monitoring and Debugging
To determine if the device is receiving a good signal and that the chip is correctly configured for its environment,
check the following status registers.
Loss of Signal – LINE.RSR.LOS – This indicates that the receiver is receiving all zeros.
Loss of Frame – T3.RSR1.LOF (or E3751.RSR1 or E3832.RSR1) – This indicates that the framer was unable to
synchronize to the incoming data. Verify that the FM bits have been correctly configured for the correct mode of
traffic (DS3, E3 G.751, E3 G.832)
Other helpful techniques to utilize in diagnosing a problem include using Line Loopback and Diagnostic Loopback.
These features help to isolate and identify the source of the problem. Line Loopback will loop the receive input to
the transmit output, eliminating the transmit side input from the equation. Diagnostic Loopback will loop the
transmit output before the line interface to the receive framer.
One other potential problem is the Line Encoding/Decoding. The device needs to be configured in the same mode
as the far end piece of equipment. If the far end piece of equipment is transmitting and receiving HDB3/B3ZS
encoded data, the DS316x also must be configured to do the same. This is controlled by the LINE.TCR.TZSD and
the LINE.RCR.RZSD bits.
9.1.1
Check the status registers of the FIFO block. Common indicators to check would be the Transmit Underflow,
Transmit Overflow, and Receive Overflow status bits. These status bits are located in the FIFO.TSRL Register and
the FIFO.RSRL Register.
the FIFO was empty.
A Transmit Overflow indicates that either a start of cell or a start of packet or a short packet was received when the
FIFO was full. Additionally, if additional packet data is received when the FIFO is already full, it will result in an
abort status for the current packet and the Transmit Overflow being declared.
A Receive Overflow occurs when cell data is received while the FIFO is full. In a packet system, the overflow will
be declared when a start of packet or a short packet is received or packet data is received when the FIFO is full
resulting in an abort status for the current packet and the Receive Overflow being declared.
9.1.2
Monitoring the Loss of Cell Delineation in the Cell Processor is recommended to insure proper operation. The LCD
status bit is located in the CP.RSR Register and indicates when an Out of Cell Delineation persists for a
programmed number of cells (set in the CP.RLTC Register).
9.1.3
Monitoring the number of errored packets in the Packet Processor is recommended for proper operation. The
REPC status bit is located in the PP.RSR Register and indicates when the errored packet count is not zero. An
errored packet is detected when an errored FCS is detected. To determine how many errored packets have been
received, the FCS Errored Packet Count Registers must first be updated via the PMU signal.
A Transmit Underflow indicates that the transmit cell processor or packet processor has attempted a read while
Cell/Packet FIFO
Cell Processor
Packet Processor
Setting