SI8441BB-D-IS Silicon Laboratories Inc, SI8441BB-D-IS Datasheet - Page 7

• Manufacturer Part Number: SI8441BB-D-IS
• Description: IC ISOLATOR 4CH 5.5V 16-SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: ISOpror

Specifications of SI8441BB-D-IS

• Number Of Channels: 4
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Inputs - Side 1/side 2: 3/1
• Isolation Rating: 2500Vrms
• Voltage - Supply: 2.7 V ~ 5.5 V
• Data Rate: 150Mbps
• Propagation Delay: 6ns
• Output Type: Tri-State
• Operating Temperature: -40°C ~ 125°C
• Mounting Style: SMD/SMT
• Propagation Delay Time: 6 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1762-5

Table 3. Electrical Characteristics (Continued)
(V
Parameter
Si844xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|t
Propagation Delay Skew
Channel-Channel Skew
All Models
Output Rise Time
Output Fall Time
Common Mode Transient
Immunity
Enable to Data Valid
Enable to Data Tri-State
Start-up Time
Notes:
PLH
DD1
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
2. t
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
= 5 V ±10%, V
- t
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
the same supply voltages, load, and ambient temperature.
PSK(P-P)
PHL
|
3,4
is the magnitude of the difference in propagation delay times measured between different units operating at
DD2
3
= 5 V ±10%, T
3
2
t
PHL
t
Symbol
PSK(P-P)
A
CMTI
PWD
t
t
t
t
PSK
= –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
en1
en2
SU
, t
t
t
r
f
PLH
Test Condition
V
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 1
See Figure 1
I
C
C
= V
L
L
= 15 pF
= 15 pF
DD
Rev. 1.3
or 0 V
Min
3.0
—
—
—
—
—
—
—
—
—
—
0
Si8440/41/42/45
Typ
6.0
1.5
2.0
0.5
3.8
2.8
5.0
7.0
25
15
—
—
Max
150
6.0
9.5
2.5
3.0
1.8
5.0
3.7
8.0
9.2
40
—
Mbps
kV/µs
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
7