SDCFH-1024-388 SanDisk, SDCFH-1024-388 Datasheet - Page 47

• Manufacturer Part Number: SDCFH-1024-388
• Description: COMPACT FLASH 1GB ULTRA II
• Manufacturer: SanDisk

Specifications of SDCFH-1024-388

• Memory Size: 1GB
• Memory Type: CompactFLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2007 SanDisk Corporation
SanDisk CompactFlash Card OEM Product Manual
4.3
Memory Mapped Addressing
When CompactFlash Memory Card registers are accessed via memory references, they appear
in the common memory space window: 0-2K bytes as shown in Table 4-4.
Table 4-4
-REG
a. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Do not care) as a word register on the
b. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1.
c. Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair
of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this
word register overlaps the address space of the Error and Feature byte-wide registers that lie at off ­
set 1. When accessed twice as byte register with CE1 low, the first byte to be accessed is the even
byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte
access to register 0 with CE1 high and CE2 low accesses the error (read) or feature (write) register.
Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the regis­
ters are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte.
Repeated byte accesses to register 8 or 0 will access consecutive (even than odd) bytes from the
data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data
buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte
accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer.
Byte accesses to register 9 access only the odd byte of the data.
between 400h and 7FFh access register 9. This 1 KByte memory window to the data register is pro­
vided so that hosts can perform memory to memory block moves to the data register when the regis ­
ter lies in memory space. Some hosts, such as the X86 processors, must increment both the source
and destination addresses when executing the memory to memory block move instruction. Some
PCMCIA socket adapters also have auto incrementing address logic embedded within them. This
address window allows these hosts and adapters to function efficiently.
Note that this entire window accesses the Data Register FIFO and does not allow random access to
the data buffer within the card.
A10
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Memory Mapped Decoding
A9-
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A3
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
A2
X
X
0
0
0
0
1
1
1
1
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
0
1
1
X
X
4-3
A0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
Offset
D
E
F
0
1
2
3
4
5
6
7
8
9
8
9
Even RD Data
Error Register
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Status
Dup Even RD Data
Dup Odd RD Data
Dup Error
Alt Status
Drive Address
Even RD Data
Odd RD Data
-OE=0
ATA Register Set and Protocol
b
c
b
a
c
b
b
Even WR Data
Features
Sector Count
Sector No.
Cylinder Low
Cylinder High
Select Card/Head
Command
Dup Even WR Data
Dup Odd WR Data
Dup Features
Device Ctl
Reserved
Even WR Data
Even RD Data
Rev. 12.0, 02/07
-WE=0
b
b
c
a
c
b
b