MT9VDDT6472AG-335D1 Micron Technology Inc, MT9VDDT6472AG-335D1 Datasheet - Page 20

• Manufacturer Part Number: MT9VDDT6472AG-335D1
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472AG-335D1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 167MHz
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1137

pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialzation, V
40. The current Micron part operates below the slow-
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
width
than 1/3 of the cycle rate. V
= -1.5V for a pulse width
can not be greater than 1/3 of the cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
equal to or less than V
may be 1.35V maximum during power up, even if
V
ohms of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
IH
DD
RPST), or begins driving (
DD
/V
overshoot: V
and V
t
DQSCK (MIN) +
DD
3ns and the pulse width can not be greater
DD
Q are 0.0V, provided a minimum of 42
DD
level and the referenced test load. In
Q must track each other.
IH
(MAX) = V
t
DD
DD
RPRE (MAX) condition.
t
RPRE begin point are not
Q, V
+ 0.3V. Alternatively, V
IL
3ns and the pulse width
t
t
LZ (MIN) will prevail
RPRE).
undershoot: V
DD
TT
t
, and V
Q+1.5V for a pulse
DQSCK (MAX) +
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
REF
IL
must be
(MIN)
TT
TT
20
41. For -40B modules, I
42. Random addressing changing and 50 percent of
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. I
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
per DDR SDRAM device at 100 MHz.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
to a valid high or low logic level. IDD2Q is similar
to I
control inputs to remain stable. Although IDD2F,
I
case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
REF later.
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-Pin DDR SDRAM UDIMM
2N specifies the DQ, DQS and DM to be driven
2N, and I
DD
2F except I
DD
2Q are similar, I
DD
DD
2Q specifies the address and
3N is specified to be 35mA
©2004 Micron Technology, Inc.
DD
2F is “worst