MT16VDDT6464AY-40BK1 Micron Technology Inc, MT16VDDT6464AY-40BK1 Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT16VDDT6464AY-40BK1
Manufacturer Part Number
MT16VDDT6464AY-40BK1
Description
MODULE DDR 512MB 200MHZ 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT16VDDT6464AY-335K1.pdf
(15 pages)
Specifications of MT16VDDT6464AY-40BK1
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184UDIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
256Mb
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Operating Current
1.632A
Number Of Elements
16
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 11:
PDF: 09005aef80739fa5/Source:09005aef807397e5
DD16C64_128_256x64A.fm - Rev. E 8/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
cycle; Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle;
Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
changing once per clock cycle; V
Active power-down standby current: One device bank active;
Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads;
One device bank active; Address and control inputs changing once per
clock cycle;
Operating burst write current: BL = 2; Continuous burst writes;
One device bank active; Address and control inputs changing once per
clock cycle;
per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t
READ or WRITE commands
CK =
RC =
CK =
CK =
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock
CK (MIN); CKE = HIGH; Address and other control inputs
CK (MIN); Address and control inputs change only during active
t
RC =
t
t
CK =
CK =
t
RAS (MAX);
I
Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
DD
t
CK =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice
Specifications and Conditions – 512MB (All Other Die Revisions)
Notes:
t
t
CK =
CK =
t
CK (MIN); I
t
t
t
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
1. Value calculated as one module rank in this operating condition; all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
OUT
IN
t
I
DD
CK (MIN); DQ, DM, and DQS inputs
= 0mA
= V
OUT
2P (CKE LOW) mode.
REF
= 0mA; Address and control
for DQ, DM, and DQS
512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
t
RC =
t
t
REFC =
REFC = 7.8125µs
t
RC =
t
RC (MIN);
t
RC (MIN);
t
RFC (MIN)
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
1,112
1,392
1,120
1,632
1,592
4,160
3,792
-40B
960
640
64
96
64
Electrical Specifications
1,032
1,392
1,432
1,432
4,080
3,312
-335
800
480
960
64
96
64
©2004 Micron Technology, Inc. All rights reserved
1,032
1,312
1,232
1,232
3,760
2,832
-262
720
400
800
64
96
64
3,760/
2,832/
-26A/
1,192
1,232
1,232
3,920
2,952
-265
400/
992
720
480
800
64
96
64
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA