MT16VDDT6464AY-40BK1 Micron Technology Inc, MT16VDDT6464AY-40BK1 Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT16VDDT6464AY-40BK1
Manufacturer Part Number
MT16VDDT6464AY-40BK1
Description
MODULE DDR 512MB 200MHZ 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT16VDDT6464AY-335K1.pdf
(15 pages)
Specifications of MT16VDDT6464AY-40BK1
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184UDIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
256Mb
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Operating Current
1.632A
Number Of Elements
16
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 13:
PDF: 09005aef80739fa5/Source:09005aef807397e5
DD16C64_128_256x64A.fm - Rev. E 8/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
and control inputs change only during active READ or WRITE commands
CK =
RC =
RC =
CK =
CK =
IN
= V
t
t
t
t
t
RC (MIN);
RAS (MAX);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
REF
t
t
CK =
CK =
for DQ, DM, and DQS
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
I
Values are for the MT46V128M8 DDR SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
DD
t
CK =
OUT
Specifications and Conditions – 2GB
t
CK =
Notes:
= 0mA
t
CK (MIN); I
t
CK (MIN); DQ, DM, and DQS inputs changing twice per
1. Value calculated as one module rank in this operating condition; all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
I
DD
OUT
2P (CKE LOW) mode.
t
RC =
= 0mA; Address and control inputs
t
RC (MIN);
512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
t
RC =
t
CK =
t
t
REFC =
REFC = 7.8125µs
t
RC (MIN);
t
t
CK =
CK (MIN); Address
13
t
t
CK (MIN);
RFC (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
Electrical Specifications
1,360
1,640
1,040
1,840
1,920
5,440
4,280
-335
160
560
800
160
144
©2004 Micron Technology, Inc. All rights reserved
1,240
1,520
1,680
1,760
5,280
3,960
-265
160
960
480
720
160
144
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA