MT18VDDF12872HG-40BD1 Micron Technology Inc, MT18VDDF12872HG-40BD1 Datasheet
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MT18VDDF12872HG-40BD1
Specifications of MT18VDDF12872HG-40BD1
Related parts for MT18VDDF12872HG-40BD1
MT18VDDF12872HG-40BD1 Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 1GB (x72, ECC, DR) PC3200 200-PIN DDR SODIMM MT18VDDF12872H – 1GB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 200-Pin SODIMM (MO-224) Height 1.25in. (31.75mm) OPTIONS • Package 200-pin SODIMM (standard) ...
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... PART NUMBER MODULE DENSITY MT18VDDF12872HG-40B__ MT18VDDF12872HY-40B__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDF12872HG-40BA1. pdf: 09005aef80e4880c, source: 09005aef80e487d7 DDAF18C128x72HG.fm - Rev. A 10/04 EN CONFIGURATION MODULE BANDWIDTH 1GB 128 Meg ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN PIN PIN SYMBOL SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DQ25 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 118, 119, 120 CAS#,RAS# 35, 37, 89, 91, 158, 160 CK0, CK0#, CK1, CK1#, CK2, CK2# ...
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... No Connect: These pins should be left unconnected. DNU — Do Not Use: These pins are not connected on this module, but are assigned pins on other modules in this product family. 5 1GB (x72, ECC, DR) PC3200 200-PIN DDR SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DQ62 DQ DQ63 DM CS# DQS U17 DDSPD REF V SS Standard modules use the following DDR SDRAM devices: MT46V64M8FN (1GB) Low-power modules use the following DDR SDRAM devices: www.micron.com/ MT46V64M8BN (1GB) 6 1GB (x72, ECC, DR) PC3200 200-PIN DDR SODIMM DM CS# DQS DM CS# DQS U19 ...
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... DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and out- put drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 1GB DD DDR SDRAM devices only; Notes: 1–5, 8, 10, 12, 46; notes appear on pages 16–18; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); DQ, DM ...
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Table 13: Capacitance Note: 11; notes appear notes appear on pages 16–18 PARAMETER Input/Output Capacitance: DQ, DQS,DM Input Capacitance: Command and Address Input Capacitance: CK, CK#, Input Capacitance: CKE, S# Table 14: DDR SDRAM Component Electrical Characteristics and Recommended AC ...
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Table 14: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 28; notes appear on pages 16–18; 0°C AC CHARACTERISTICS PARAMETER ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). The data valid window ...
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The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure ...
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Table 15: EEPROM Device Select Code Most significant bit (b7) is sent first. SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 16: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 17: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 19: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 0 Number of Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Rows Addresses on ...
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Table 19: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 41 Minimum Active Auto Refresh Time, 42 Minimum Auto Refresh to Active/Auto Refresh Command t Period, RFC 43 SDRAM Device Max Cycle Time, 44 ...
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Figure 15: 200-PIN SODIMM Dimensions 0.079 (2.00 (2X) 0.071 (1.80) U5 (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (0 .99) TYP PIN 1 U11 U15 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation ...