MT16VDDT6464AG-40BG6 Micron Technology Inc, MT16VDDT6464AG-40BG6 Datasheet - Page 18

• Manufacturer Part Number: MT16VDDT6464AG-40BG6
• Description: MODULE DDR 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT6464AG-40BG6

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.632A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 16: Capacitance
Note: 11; notes appear on pages 20–23
Table 17: DDR SDRAM Component Electrical Characteristics and Recommended
Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/
CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/
CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
Write command to first DQS latching transition
DQS falling edge to CK rising -
setup time
DQS falling edge from CK rising -
hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew
rate)
Address and control input setup time (fast slew
rate)
Address and control input hold time (slow slew
rate)
PARAMETER
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: S#, CKE
Input Capacitance: CK0, CK0#
Input Capacitance: CK1, CK1#; CK2, CK2#
AC Operating Conditions
CL = 2.5
CL = 2
SYMBOL
t
t
CK (2.5)
t
t
t
t
DQSCK
t
t
CK (2)
DQSQ
DQSH
DIPW
t
DQSL
DQSS
t
t
t
t
DSH
t
t
t
t
t
t
DSS
t
t
DH
AC
CH
DS
HP
HZ
IH
IH
CL
IS
LZ
F
F
S
-0.60
-0.70
18
256MB, 512MB, 1GB, 2GB (x64, DR)
MIN
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
0.80
-0.7
7.5
0.2
0.2
6
t
CH,
-335
T
A
t
CL
+0.60
+0.70
MAX
+0.7
0.55
0.55
0.45
1.25
+70°C; V
13
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
7.5/10
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
SYMBOL
7.5
0.5
0.5
0.2
0.2
DD
1
t
CH,
C
C
C
C
C
-262
= V
IO
I
I
I
I
1
1
2
3
t
DD
CL
+0.75
+0.75
+0.75
MAX
0.55
0.55
1.25
0.5
13
13
Q = +2.5V ±0.2V
7.5/10
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
7.5
0.5
0.5
0.2
0.2
.90
.90
-26A/-265
1
t
CH,
MIN
32
16
11
12
8
t
CL
+0.75
+0.75
+0.75
MAX
0.55
0.55
1.25
0.5
13
13
MAX
10
48
24
15
18
©2004 Micron Technology, Inc.
UNITS NOTES
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
UNITS
pF
pF
pF
pF
pF
41, 46
41, 46
23, 27
23, 27
22, 23
16, 37
16, 37
26
26
27
31
12
12
12