MT18VDDT12872AG-335F1 Micron Technology Inc, MT18VDDT12872AG-335F1 Datasheet - Page 13
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MT18VDDT12872AG-335F1
Manufacturer Part Number
MT18VDDT12872AG-335F1
Description
MODULE DDR 1GB 184-DIMM
Manufacturer
Micron Technology Inc
Specifications of MT18VDDT12872AG-335F1
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
333MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184UDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.62A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 12: I
DDR SDRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
PARAMETER/CONDITION
NOTE:
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cyle; Address and control inputs changing
once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 2;
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
changing once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs
(BL = 4) with auto precharge,
Address and control inputs change only during Active READ, or
WRITE commands
RC =
CK =
a: Value calculated as one module rank in this operating condition, and all other module ranks in I
b: Value calculated reflects all module ranks in this operating condition.
t
t
t
RC (MIN);
CK MIN; CKE = HIGH; Address and other control inputs
CK =
t
RC =
t
t
CK =
CK (MIN); I
t
DD
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
Specifications and Conditions – 256MB
t
CK (MIN); DQ, DM and DQS inputs
OUT
t
RC =
t
CK =
t
t
CK =
CK =
= 0mA
t
t
RC =
RAS (MAX);
t
0.2V
t
CK (MIN); CKE = (LOW)
IN
CK (MIN); CKE = LOW
t
CK (MIN); I
= V
t
RC (MIN);
REF
for DQ, DQS, and DM
t
CK =
OUT
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
t
CK =
t
t
= 0mA; Address
REFC =
REFC = 15.625µs
t
CK (MIN); DQ,
t
CK (MIN);
t
RFC (MIN)
T
A
13
+70°C; V
I
I
I
DD
I
I
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
DD4W
SYM
I
I
DD3N
I
DD5A
I
I
DD2P
DD2F
DD3P
DD4R
184-PIN DDR SDRAM UDIMM
DD0
DD1
DD5
DD6
DD7
= V
a
a
b
b
a
b
b
b
b
a
b
a
DD
Q = +2.6V ±0.1V
MAX
1,062
1,242
1,242
1,422
2,160
3,222
-40B
450
225
450
27
54
36
DD
2
P
UNITS
(CKE LOW) mode.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
©2004 Micron Technology, Inc.
NOTES
21, 28,
21, 28,
21, 41
21, 41
21, 41
24, 43
20, 42
43
44
43
21
43
9