MT8VDDT3264HY-335G3 Micron Technology Inc, MT8VDDT3264HY-335G3 Datasheet - Page 10
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MT8VDDT3264HY-335G3
Manufacturer Part Number
MT8VDDT3264HY-335G3
Description
MODULE DDR SDRAM 256MB 200SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT8VDDT3264HY-335G3
Memory Type
DDR SDRAM
Memory Size
256MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
256Mb
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.4A
Number Of Elements
8
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
DLL Enable/Disable
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE HIGH must occur before a
READ command can be issued.
pdf: 09005aef8092973f, source: 09005aef80921669
DD8C16_32_64x64HG.fm - Rev. B 9/04 EN
The extended mode register must be loaded when
The DLL must be enabled for normal operation.
10
128MB Module
NOTE:
256MB, 512MB Modules
128MB, 256MB, 512MB (x64, SR)
1. BA1 and BA0 (E13 and E12 for 128MB or E14 and E13
2. QFC# is not supported.
E11
0
14
0
–
BA1 BA0
1
for 256MB and 512MB) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Register).
Figure 6: Extended Mode Register
E10
0
1
13
BA1 BA0
13
1
0
–
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
E9
12
1
12
0
–
A12
11
E8
11
0
A11
–
A11
E7
10
0
–
10
A10
A10
Definition Diagram
Operating Mode
E6 E5
0
–
9
9
A9
A9
Operating Mode
200-PIN DDR SODIMM
0
–
8
A8
8
A8
E4
0
–
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
E3
0
–
6
6
E2
0
–
5
2
5
©2004 Micron Technology, Inc. All rights reserved.
4
4
E1,
Valid
–
3
E0
3
2
2
A2 A1 A0
A2 A1 A0
DS
DS
Operating Mode
Normal Operation
All other states reserved
1
1
E1
0
DLL
DLL
0
0
E0
0
1
Extended Mode
Register (Ex)
Drive Strength
Extended Mode
Register (Ex)
Address Bus
Address Bus
Normal
Disable
Enable
DLL