MT18VDDF12872HY-335D1 Micron Technology Inc, MT18VDDF12872HY-335D1 Datasheet - Page 14
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MT18VDDF12872HY-335D1
Manufacturer Part Number
MT18VDDF12872HY-335D1
Description
MODULE SDRAM DDR 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDDF12872HY-335D1.pdf
(27 pages)
Specifications of MT18VDDF12872HY-335D1
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.53A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 13: I
Notes: 1–5, 8, 10, 12, 47; DDR SDRAM devices only; notes appear on pages 17–20; 0°C £ T
09005aef80e487d7
DDF18C64_128x72HG_A.fm - Rev. A 10/03 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4;
0mA; Address and control inputs
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are
idle;
inputs changing once per clock
and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
device bank active
and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2;
device bank active; Address and control inputs changing once
per clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank
once per clock cycle;
changing twice per clock cycle
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE £ 0.2V
OPERATING CURRENT: Four device bank interleaving READs
(Burst = 4) with auto precharge,
t
Active READ, or WRITE commands
NOTE:
RC =
CK =
a - Value calculated as one module rank in this operating condition, and all other module ranks in I
b - Value calculated reflects all module ranks in this operating condition.
t
CK =
t
t
CK (MIN); Address and control inputs change only during
RC (MIN);
t
CK (MIN);
t
CK =
DD
t
CK =
active; Address and control inputs changing
;
t
RC =
Specifications and Conditions – 1GB
t
t
CK =
CK (MIN);
t
CKE = HIGH; Address and other control
RC =
t
CK (MIN); DQ, DM and DQS inputs
t
RAS (MAX);
t
CK (MIN); DQ, DM, and DQS inputs
t
t
RC (MIN);
CK =
cycle. V
I
t
OUT
RC = minimum
t
CK =
Reads; Continuous burst; One
t
changing once per clock
CK (MIN); CKE = LOW
= 0mA
t
CK =
IN
t
t
CK (MIN);
CK =
= V
t
t
CK (MIN); DQ, DM
REF
RC =
t
CK (MIN); I
t
RC = 7.8125µs
t
for DQ, DQS,
RC allowed;
t
CKE = (LOW)
RFC (MIN)
One
OUT
14
=
I
I
I
I
I
I
I
SYM
DD4W
I
I
DD3N
I
DD5A
I
I
DD2P
DD2F
DD3P
DD4R
DD0
DD1
DD5
DD6
DD7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MB, 1GB (x72, ECC, DR)
1,215
1,485
1,530
1,440
5,220
3,690
-335
810
630
810
180
90
90
200-PIN DDR SODIMM
MAX
1,215
1,485
1,530
1,440
5,220
3,645
A
-262
810
630
810
180
90
90
£ +65°C; V
-26A/
1,080
1,350
1,350
1,260
5,040
3,195
-265
720
540
720
180
DD
90
90
DD
, V
2p (CKE LOW) mode.
DD
©2003 Micron Technology, Inc.
Q = +2.5V ±0.2V
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 41
20, 41
20, 41
20, 43
24, 43
20, 42
43
44
43
20
9