MT36LSDF12872G-133D1 Micron Technology Inc, MT36LSDF12872G-133D1 Datasheet - Page 4

• Manufacturer Part Number: MT36LSDF12872G-133D1
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872G-133D1

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5:
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
74–77, 86–89, 91–95, 97–101,
28, 29, 46, 47, 112, 113, 130,
21, 22, 52, 53, 105, 106, 136,
149–151, 153–156, 158–161
33–38, 117–121, 123, 126
55–58, 60, 65–67, 69–72,
2–5, 7–11, 13–17, 19–20,
103–104, 139–142, 144,
42, 79, 125, 163
30, 45, 114, 129
Pin Numbers
27, 111, 115
165–167
39, 122
128
131
147
137
Pin Descriptions
Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information
83
82
RAS#, CAS#, WE#
DQMB0–DQMB7
DQ0–DQ63
BA0, BA1
CK0–CK3
SA0–SA2
CB0–CB7
Symbol
S0#–S3#
A0–A12
REGE
CKE0
SDA
SCL
Output
Output
Output
Input/
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK0 is distributed through an on-board PLL to all
devices. CK1–CK3 are terminated.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: S# enable (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when
S# are registered HIGH. S# are considered part of the
command code.
Input/Output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to
configure the presence-detect device.
Register enable: REGE permits the DIMM to operate in
“buffered” mode (LOW) or “registered” mode (HIGH).
Data I/Os: Data bus.
Check bits.
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and data out of the presence-
detect portion of the module.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
Description
©2002 Micron Technology, Inc. All rights reserved.