MT36LSDT25672G-13EC2 Micron Technology Inc, MT36LSDT25672G-13EC2 Datasheet - Page 13

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MT36LSDT25672G-13EC2

Manufacturer Part Number
MT36LSDT25672G-13EC2
Description
MODULE SDRAM 2GB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT36LSDT25672G-13EC2

Memory Type
SDRAM
Memory Size
2GB
Speed
133MHz
Package / Case
168-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Commands
Table 8:
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
SDRAM Command and DQMB Operation Truth Table
CKE is HIGH for all commands shown except Self Refresh
Name (Function)
Notes: 1. A0–A12 provide device row address. BA0, BA1 determine which device bank is made
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. For a more detailed description of commands and opera-
tions refer to the 256Mb or 512Mb SDRAM component data sheets.
2. A0–A9, A11 (1GB) or 0–A9, A11, A12 (2GB) provide device column address; A10 HIGH
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both
4. This command is Auto Refresh if CKE is HIGH, Self Refresh if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
6. A0–A12 define the op-code written to the Mode Register, and should be driven low.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
active.
enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto pre-
charge feature; BA0, BA1 determine which device bank is being read from or written to.
device banks are precharged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay).
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
CS#
13
H
L
L
L
L
L
L
L
L
RAS# CAS# WE# DQMB
H
H
H
H
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
X
H
H
H
H
L
L
L
L
L/H
L/H
X
X
X
X
X
X
X
H
L
7
7
©2002 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
Commands
High-Z
Active
Active
Valid
DQs
X
X
X
X
X
X
X
Notes
4, 5
1
2
2
3
6
7
7

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