MT9VDDT6472AY-335D1 Micron Technology Inc, MT9VDDT6472AY-335D1 Datasheet
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MT9VDDT6472AY-335D1
Specifications of MT9VDDT6472AY-335D1
Related parts for MT9VDDT6472AY-335D1
MT9VDDT6472AY-335D1 Summary of contents
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... RCD and RP for -335 modules show 18ns to align with industry specifications; Micron Technology, Inc., reserves the right to change products or specifications without notice. 1 184-Pin UDIMM (MO-206) 2 ≤ +70°C) A ≤ +85° Contact Micron for industrial temperature module offerings ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Table 2: Addressing Parameter Refresh count Row address Device bank address Device configuration Column address Module rank address Table 3: Part Numbers and Timing Parameters – 128MB Base device: MT46V16M8, ...
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... MT9VDDT6472AG-335__ MT9VDDT6472AY-335__ MT9VDDT6472AG-262__ MT9VDDT6472AG-265__ MT9VDDT6472AY-265__ Notes: 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272AY-335G4. ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Table 6: Pin Assignments 184-Pin DDR UDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ17 47 REF 2 DQ0 25 DQS2 ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Table 7: Pin Descriptions Symbol A0–A12 BA0, BA1 CK0, CK0#, CK1, CK1#, CK2, CK2# CKE0 DM0–DM7 RAS#, CAS#, WE# S0# SA0–SA2 SCL CB0–CB7 DQ0–DQ63 DQS0–DQS8 SDA ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Functional Block Diagram Figure 2: Functional Block Diagram BA0, BA1 A0–A11/A12 PDF: 09005aef808f912d/Source: 09005aef808f8ccd DD9C16_32_64x72A.fm - Rev. E 11/07 EN S0# DQS0 DM9 DM CS# DQS DQ0 DQ DQ1 DQ ...
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... The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit- wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n- bit-wide, one-half-clock-cycle data transfers at the I/O pins ...
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... Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’ ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM I Specifications DD Table 10: I Specifications and Conditions – 128MB DD Values are shown for the MT46V16M8 DDR SDRAM only and are computed from values specified in the 128Mb ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Table 11: I Specifications and Conditions – 256MB DD Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Table 12: I Specifications and Conditions – 512MB DD Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the 512Mb (64 Meg x ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Serial Presence-Detect Table 13: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: ...
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ECC, SR): 184-Pin DDR SDRAM UDIMM Module Dimensions Figure 3: 184-pin DDR UDIMM 2.0 (0.079) R (4X 2.5 (0.098) D (2X) 2.3 (0.091) TYP Pin 1 2.21 (0.087) TYP 1.27 (0.05) 1.0 (0.039) TYP ...