MT9VDDT6472AY-335D1 Micron Technology Inc, MT9VDDT6472AY-335D1 Datasheet - Page 9

• Manufacturer Part Number: MT9VDDT6472AY-335D1
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472AY-335D1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Table 10:
PDF: 09005aef808f912d/Source: 09005aef808f8ccd
DD9C16_32_64x72A.fm - Rev. E 11/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
cycle; Address and control inputs changing once every two clock
cycles
Operating one bank active-read-precharge current: BL = 2;
t
inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle;
Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
changing once per clock cycle. V
Active power-down standby current: One device bank active;
Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device
bank active;
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
Operating burst READ current: BL = 2; Continuous burst READs;
One device bank active; Address and control inputs changing once
per clock cycle;
Operating burst WRITE current: BL = 2; Continuous burst WRITEs;
One device bank active; Address and control inputs changing once
per clock cycle;
twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave READ current: Four device bank
interleaving READs (BL = 4) with auto precharge;
t
active READ or WRITE commands
DD
CK =
RC =
CK =
CK =
Specifications
t
t
t
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
RC (MIN);
CK (MIN); CKE = HIGH; Address and other control inputs
CK (MIN); Address and control inputs change only during
t
RC =
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Values are shown for the MT46V16M8 DDR SDRAM only and are computed from values specified in the
128Mb (16 Meg x 8) component data sheet
DD
t
t
CK =
CK =
t
CK =
Specifications and Conditions – 128MB
t
RAS (MAX);
t
t
CK =
CK =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing
t
CK (MIN); I
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
128MB, 256MB, 512MB (x72, ECC, SR): 184-Pin DDR SDRAM UDIMM
t
CK =
IN
OUT
OUT
= V
= 0mA
t
REF
= 0mA; Address and control
CK (MIN); DQ, DM, and DQS
for DQ, DM, and DQS
t
t
REFC =
REFC = 15.625µs
t
RC =
t
RC =
t
RC (MIN);
t
t
RFC (MIN)
RC (MIN);
9
Symbol
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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DD
DD
I
I
I
DD
DD
DD
I
I
I
DD
D
DD
DD
DD
DD
DD
5A
4W
3N
4R
2P
2F
3P
0
1
5
6
7
1,035
1,215
1,215
1,395
2,160
3,195
-40B
450
225
450
27
54
36
Electrical Specifications
1,125
1,215
1,260
1,260
2,385
3,195
-335
405
225
450
27
45
27
©2003 Micron Technology, Inc. All rights reserved.
1,080
1,170
1,125
1,980
2,970
-262
990
405
225
450
27
45
27
-26A/
1,080
1,125
1,080
1,980
2,925
-265
945
360
180
405
27
45
18
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA