MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 13

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
COMMAND
ADDRESS
DQS
V
DM
ODT
DQ
V
CK#
CKE
DD
V
V
V
Rtt
DDL
CK
TT
REF
DD
9
Q
1
7
7
7
LVCMOS
LOW LEVEL
DON’T CARE
High-Z
High-Z
High-Z
t
VTD
1
8
T0
t
LOW LEVEL
SSTL_18
DDR2 Power-Up and Initialization
CL
Power-up:
V
clock (CK, CK#)
DD
t
CK
and stable
T = 200µs (min)
Indicates a break in
time scale
t
CL
8
Notes: 1. V
NOP 2
Ta0
10. Bits E7, E8, and E9 must be set to 1 to set OCD default.
11. Bits E7, E8, and E9 must be set to 0 to set OCD exit and all other operating parameters of
T = 400ns (min)
2. Either a NOP or DESELECT command may be applied.
3. 200 cycles of clock (CK, CK#) are required before a READ command can be issued. CKE
4. Two or more REFRESH commands are required.
5. Bits E7, E8, and E9 must all be set to 0 with all other operating parameters of EMRS set as
6. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command,
7. DM represents all DM. DQS represents all DQS, DQS#, RDQS,and RDQS# (RDQS/RDQS# only
8. CKE pin uses LVCMOS input levels prior to state T0. After state T0, CKE pin uses SSTL_18
9. A10 should be HIGH at states Tb0 and Tg0 to ensure a PRECHARGE (all banks) command is
zero to avoid device latch-up.
The time from when V
to or less than 20ms. One of the following two conditions (A or B) MUST be met:
must be HIGH the entire time.
required.
ACT = ACTIVE command, RA = Row Address, BA = Bank Address.
functional on RDIMMs using x8 components). DQ represents all DQ.
input levels.
issued.
EMRS set as required.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
A.
B.
TT
A10 = 1
Tb0
PRE
is not applied directly to the device; however,
V
V
V
Apply V
Apply V
between any V
t
Apply V
RPA
DD
TT
REF
EMR(2)
CODE
Tc0
LM
, V
may be 0.95V maximum during power up.
tracks V
t MRD
DD
DD
DD
DD
L, and V
L before or at the same time as V
Q before or at the same time as V
EMR(3)
CODE
Td0
LM
before or at the same time as V
DD
t MRD
DD
Q/2.
DD
DLL Enable
DD
EMR with
supply can not exceed 0.3V.
CODE
Te0
LM
first starts to power-up to the completion of V
Q are driven from a single power converter output.
t MRD
13
5
DLL Reset
MR with
CODE
Tf0
LM
t MRD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A10 = 1
Tg0
PRE
t
RPA
200 cycles of CK
Th0
REF
DD
t RFC
DD
t
TT
VTD should be greater than or equal to
L.
3
Q.
and V
See note 4
REF
Ti0
t RFC
REF
©2004, 2005 Micron Technology, Inc. All rights reserved.
DLL Reset
MR w/o
CODE
. The voltage difference
Tj0
LM
t MRD
OCD Default 10
EMR with
CODE
Tk0
LM
DD
t MRD
Initialization
Q must be equal
OCD Exit 11
EMR with
CODE
LM
Tl0
t MRD
Operation
Normal
VALID
VALID 3
Tm0
See
note
3