MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 17

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Down Mode
CAS Latency
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Active power-down (PD) mode is defined by bit M12 as shown in Figure 5 on page 15.
PD mode allows the user to determine the active power-down mode, which determines
performance vs. power savings. PD mode bit M12 does not apply to precharge power-
down mode.
When bit M12 = 0, standard active power-down mode or ‘fast-exit’ active power-down
mode is enabled. The
timing. The DLL is expected to be enabled and running during this mode.
When bit M12 = 1, a lower power active power-down mode or ‘slow-exit’ active power-
down mode is enabled. The
exit timing. The DLL can be enabled, but ‘frozen’ during active power-down mode since
the exit-to-READ command timing is relaxed. The power difference expected between
PD ‘normal’ and PD ‘low-power’ mode is defined in the I
The CL is defined by bits M4–M6 as shown in Figure 5. CL is the delay, in clock cycles,
between the registration of a READ command and the availability of the first bit of out-
put data. The CL can be set to 3, 4, or 5 clocks. CL of 6 clocks is a JEDEC optional feature
and may be enabled in future speed grades. DDR2 SDRAM devices do not support any
half-clock latencies. Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
DDR2 SDRAM devices also support a feature called posted CAS additive latency (AL).
This feature allows the READ command to be issued prior to
internal command to the DDR2 SDRAM device by AL clocks. The AL feature is described
in more detail in the Extended Mode Register (EMR) and Operational sections.
Examples of CL = 3 and CL = 4 are shown in Figure 6, CAS Latency; both assume AL = 0. If
a READ command is registered at clock edge n, and the CAS latency is m clocks, the data
will be available nominally coincident with clock edge n + m (this assumes AL = 0).
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
t
XARD parameter is used for ‘fast-exit’ active power-down exit
t
XARDS parameter is used for ‘slow-exit’ active power-down
17
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DD
©2004, 2005 Micron Technology, Inc. All rights reserved.
table.
t
RCD(MIN) by delaying the
Mode Register (MR)