MT16HTS25664HY-53EA1 Micron Technology Inc, MT16HTS25664HY-53EA1 Datasheet - Page 4

• Manufacturer Part Number: MT16HTS25664HY-53EA1
• Description: MODULE DDR2 2GB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16HTS25664HY-53EA1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 533MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5:
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
98, 99, 100, 101, 102, 105
89, 90, 91, 92, 93, 94, 97,
10, 26, 52, 67, 130, 147,
30, 32, 164, 166
Pin Numbers
108, 109, 113
85, 106, 107
114, 119
110, 115
170, 185
79, 80
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
RAS#, CAS#, WE#
BA0, BA1, BA2
ODT0, ODT1
CKE0, CKE1
DM0–DM7
CK0, CK0#
CK1, CK1#
Symbol
S0#, S1#
A0–A13
Input
Input
Input
Input
Input
Input
Input
Input
Type
On-Die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides precharge power-down and SELF
REFRESH operations (all device banks idle), or active power-
down (row active in any device bank). CKE is synchronous for
power-down entry, power-down exit, output disable, and for
self refresh entry. CKE is asynchronous for self refresh exit. Input
buffers (excluding CK, CK#, CKE, and ODT) are disabled during
power-down. Input buffers (excluding CKE) are disabled during
self refresh. CKE is an SSTL_18 input but will detect a LVCMOS
LOW level once V
has become stable during the power on and initialization
sequence, it must be maintained for proper operation of the
CKE receiver. For proper SELF REFRESH operation V
maintained to this input.
Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# provides for external
rank selection on systems with multiple ranks. S# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1/BA2 define which mode register, including
MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD
MODE command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
4
Module Pin Assignments and Descriptions
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
is applied during first power-up. After V
Description
©2006 Micron Technology, Inc. All rights reserved.
REF
must be
REF