MT36HTS51272FY-53EA3D3 Micron Technology Inc, MT36HTS51272FY-53EA3D3 Datasheet - Page 22

• Manufacturer Part Number: MT36HTS51272FY-53EA3D3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-53EA3D3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 533MT/s
• Package / Case: 240-FBDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10:
Table 11:
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
Parameter
Reference clock frequency
Rise time, fall time
Voltage high
Voltage low
Absolute crossing point
Relative crossing point
Percent mismatch between rise and fall times T
Duty cycle of reference clock
Clock leakage current
Clock input capacitance
Clock input capacitance delta
Transport delay
Phase jitter sample size
Reference clock jitter, filtered
Reference clock deterministic jitter
Idle current, DDR2 SDRAM device power-down
Active power, 50% DDR2 SDRAM BW
Reference Clock Input Specifications
V
TT
Currents
Notes:
Description
10. The net transport delay is the difference in time of flight between associated data and clock
11. Direct measurement of phase jitter records over 1,016 periods is impractical. It is expected
12. Measured with SSC-enabled on reference clock generator.
13. As measured after the phase jitter filter. This number is separate from the receiver jitter
1. 133 MHz for PC2-4200 and 166 MHz for PC2-5300.
2. Measured with SSC disabled.
3. Measured differentially through the range of 0.175V to 0.525V.
4. The crossing point must meet the absolute and relative crossing point specification simulta-
5. V
6. Measured with a single-ended input voltage of 1V.
7. Applies to reference clocks SCK and SCK#.
8. Difference between SCK and SCK# input.
9. T1 = |Tdatapath - Tclockpath| (excluding PLL loop delays). This parameter is not a direct
neously.
0.5 (V
age of V
clock output parameter but it indirectly determines the clock output parameter T
paths. The data path is defined from the reference clock source, through the TX, to data
arrival at the data sampling point in the RX. The clock path is defined from the reference
clock source to clock arrival at the same sampling point. See Figure 3-3 of the JEDEC specifi-
cation. The path delays are caused by copper trace routes, on-chip routing, on-chip buffer-
ing, etc. They include the time-of-flight of interpolators or other clock adjustment
mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth
because these delays are modeled by the PLL transfer functions.
that the jitter will be measured over a smaller, yet statistically significant, sample size and
the total jitter at 10
jitter components.
budget that is defined by the TRXTotal-MIN parameters.
CROSS
HAVG
_
REL
SCK
_(
- 0.710) + 0.250; and MAX = 0.5 (V
-
MIN
HIGHM
) and V
T
SCK
.
SCK
T
16
SCK
-
V
V
-
RISE
NSAMPLE
T
V
V
Symbol
RISE
samples extrapolated from an estimate of the sigma of the random
CROSS
C
REF
CROSS
CROSS
SCK
T
SCK
-
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
I
DUTYCYCLE
C
REF
_
f
I
-
I
T1
SCK
-
I
CK
-
, T
FALL
-
-
CK
JITTER
-
CK
HIGH
LOW
-
(
-
DJ
SCK
-
_
D
ABS
REL
22
REL
-
)
MATCH
-
FALL
_(
MAX
Symbol
) are derived using the following calculation: MIN =
I
I
TT
TT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
calculated
1
2
133.33
–0.25
–150
Min
10
175
660
250
–10
0.5
40
I
–
–
–
HAVG
DD
16
Specifications and Conditions
- 0.710) + 0.550, where V
Typ
500
500
calculated
Max
0.25
TBD
200
700
850
550
10
60
10
40
2
5
–
©2006 Micron Technology, Inc. All rights reserved.
Max
700
700
Periods
Unit
MHz
mV
mV
mV
µA
pF
pF
ps
%
%
ns
ps
ps
–
HAVG
Preliminary
is the aver-
Unit
REF
mA
mA
Notes
12, 13
9, 10
-
1, 2
4, 5
6, 7
JITTER
11
3
4
7
8
.