MT8JTF12864AY-1G4D1 Micron Technology Inc, MT8JTF12864AY-1G4D1 Datasheet - Page 4

• Manufacturer Part Number: MT8JTF12864AY-1G4D1
• Description: MODULE DDR3 SDRAM 1GB 240-UDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8JTF12864AY-1G4D1

• Memory Type: DDR3 SDRAM
• Memory Size: 1GB
• Speed: 1333MT/s
• Package / Case: 240-UDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6:
PDF: 09005aef82b21119/Source: 09005aef82b2112c
JTF8c128_256x64AY.fm - Rev. B 6/08 EN
RAS#, CAS#,
DQS#[7:0]
CK0#[1:0]
DQS[7:0],
DQ[63:0]
Symbol
DM[7:0]
CK[1:0],
V
A[14:0]
BA[2:0]
RESET#
SA[2:0]
V
V
ODT0
CKE0
REF
WE#
REF
SDA
DDSPD
V
SCL
S0#
V
V
NC
DD
TT
SS
DQ
CA
Pin Descriptions
Supply Power supply: 1.5V ±0.075V.
Supply Serial EEPROM positive power supply: +3.0V to +3.6V.
Supply Reference voltage: DQ, DM (V
Supply Reference voltage: Control, command, and address (V
Supply Ground.
Supply Termination voltage: Used for control, command, and address (V
Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and
Input Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE, or
Input Clock: CK0 and CK0# are differential clock inputs. All contorl, command, and address input signals
Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is
Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR3
Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
Input Reset: RESET# is an active LOW CMOS input referenced to V
Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM address range.
Input Serial clock for presence-detect: SCL is used to synchronize presence-detect data transfer to
Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
Type Description
I/O
I/O
I/O
–
auto precharge bit for READ/WRITE commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine whether the
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands.. The address inputs also provide the op-code during the mode register
command set
PRECHARGE command is being applied. BA[2:0] define which mode register, including MR, EMR,
EMR(2), and EMR(3), is loaded during the LOAD MODE command.
are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data
(DQ and DQS/DQS#) is referenced to the crossings of CK and CK#. CK1, CK1# are terminated.
circuitry on the DDR3 SDRAM.
sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is designed to match that of the DQ and DQS
pins.
SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,DQS#, and DM. The ODT
input will be ignored if disabled via the LOAD MODE command.
input and is defined as a rail-to-rail signal with DC HIGH ≥ 0.8 x V
assertion and desertion are asynchronous.
and from the module.
With both inputs HIGH, all outputs of the register(s) are disabled except for CKE and ODT. CKE, ODT
and chip select remain in previous state when both outputs are high.
Data input/output: Bidirectional data bus.
Data strobe: Output with read data. Input with write data for source-synchronous operation. Edge-
aligned with read data. Center-aligned with write data. DQS# is only used when the differential
data strobe mode is enabled via the LOAD MODE command.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the SPD EEPROM on the module.
No connect: These pins are not connected on the module.
.
A[13:0] (1GB), A[14:0] (2GB).
1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
DD
/2).
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
DD
/2).
SS
. The RESET# input receiver is a CMOS
DD
DD
and DC LOW ≤ 0.2 x V
/2).
©2007 Micron Technology, Inc. All rights reserved
DD
. RESET#