HSC-ADC-EVALCZ Analog Devices Inc, HSC-ADC-EVALCZ Datasheet - Page 26

• Manufacturer Part Number: HSC-ADC-EVALCZ
• Description: KIT EVAL ADC FIFO HI SPEED
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-EVALCZ

• Design Resources: EVALC PC Board Gerber File
• Accessory Type: ADC Interface Board
• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Features: Buffer Memory Board For Capturing Digital Data, USB Port Interface, Windows 98, Windows 2000
• Kit Contents: ADC Analyzer, Buffer Memory Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Single ADC Version
• Lead Free Status / Rohs Status: Supplier Unconfirmed

HSC-ADC-EVALC
Table 3. HSC-ADC-EVALC J1 I/O Connections to FPGA (U1)
Connector J1
(HS-Serial, SPI, AUX)
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
A5
B5
C5
D5
A6
B6
C6
D6
A7
B7
C7
D7
A8
B8
C8
D8
A9
B9
C9
D9
A10
B10
C10
D10
Schematic Net Name
USB_5
USB_4
MGTCLK2+
MGTCLK2−
USB_3
USB_2
none
none
CSB_4
USB_1
none
none
CSB_3
SDO
none
none
CSB_2
SDI
none
none
CSB_1
SCLK
SD4+
SD4−
I/O_8
I/O_7
SD3+
SD3−
I/O_6
I/O_5
SD2+
SD2−
I/O_4
I/O_3
SD1+
SD1−
I/O_2
I/O_1
MGTCLK1+
MGTCLK1−
FPGA Pin
none
none
AF10
AF11
none
none
none
none
none
none
none
none
none
H12
none
none
none
K12
none
none
none
H13
AF7
AF8
AD3
AC3
AC1
AD1
AA3
Y3
G1
H1
W3
V3
A4
A3
P3
N3
K1
L1
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Table 4. HSC-ADC-EVALC J2 I/O Connections to FPGA (U1)
Connector J2
(DATA BUS 1)
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
A5
B5
C5
D5
A6
B6
C6
D6
A7
B7
C7
D7
A8
B8
C8
D8
A9
B9
C9
D9
A10
B10
C10
D10
Schematic Net Name
DCLKB2+
DCLKB2−
D0B+
D0B−
D1B+
D1B−
D2B+
D2B−
D3B+
D3B−
D4B+
D4B−
D5B+
D5B−
D6B+
D6B−
D7B+
D7B−
D8B+
D8B−
D9B+
D9B−
D10B+
D10B−
D11B+
D11B−
D12B+
D12B−
D13B+
D13B−
D14B+
D14B−
D15B+
D15B−
D16B+
D16B−
DCLKB1+
DCLKB1−
D17B+
D17B−
FPGA Pin
C13
C12
T4
T3
M4
N4
P4
R3
M5
L5
L4
L3
K3
J3
L7
M6
J4
H3
K6
J5
G5
F4
H4
G4
H8
H7
G7
H6
F8
F7
K8
K7
B9
A9
A8
A7
A12
B12
B10
A10