HSC-ADC-EVALCZ Analog Devices Inc, HSC-ADC-EVALCZ Datasheet - Page 5

• Manufacturer Part Number: HSC-ADC-EVALCZ
• Description: KIT EVAL ADC FIFO HI SPEED
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-EVALCZ

• Design Resources: EVALC PC Board Gerber File
• Accessory Type: ADC Interface Board
• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Features: Buffer Memory Board For Capturing Digital Data, USB Port Interface, Windows 98, Windows 2000
• Kit Contents: ADC Analyzer, Buffer Memory Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Single ADC Version
• Lead Free Status / Rohs Status: Supplier Unconfirmed

JUMPERS
Default Settings
Table 1 lists the default settings for the HSC-ADC-EVALC evaluation kit.
Table 1. Jumper Configurations
Jumper Number
J9, Pin 1 to Pin 2 (1.8 V)
J9, Pin 3 to Pin 4 (2.5 V)
J9, Pin 5 to Pin 6 (3.3 V)
Table 2. FPGA Configuration Mode
U4 DIP Switch Setting
FPGA Configured via EEPROM
FPGA Configured via USB (Default)
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
ROHDE & SCHWARZ,
ROHDE & SCHWARZ,
2V p-p SIGNAL
SYNTHESIZER
2V p-p SIGNAL
SYNTHESIZER
Figure 2. Example Setup Using ADC Evaluation Board and HSC-ADC-EVALC ADC Capture Board
SMHU,
SMHU,
SWITCHING
POWER
SUPPLY
BAND-PASS
FILTER
Description
Default. Sets FPGA I/O voltage to 1.8 V logic (hardwired, do not remove).
Install single jumper here to set FPGA I/O voltage to 2.5 V logic.
Install single jumper here to set FPGA I/O voltage to 3.3 V logic.
XFMR
INPUT
CLK
EVALUATION
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BOARD
M0
On
On
DATA BUS 2
LVDS/CMOS
DATA BUS 1
LVDS/CMOS
PARALLEL
PARALLEL
OUTPUTS
OUTPUTS
SPI
3A MAX
5V DC
M1
On
Off
ONBOARD POWER
HSC-ADC-EVALC
DATA CAPTURE
SPI
SUPPLY
BOARD
–
CONNECTION
PS
+
USB
M2
On
Off
VisualAnalog
RUNNING
PC
M3
Reserved
Reserved
HSC-ADC-EVALC
M4
Reserved
Reserved