ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet
ADZS-21262-1-EZEXT
Specifications of ADZS-21262-1-EZEXT
Related parts for ADZS-21262-1-EZEXT
ADZS-21262-1-EZEXT Summary of contents
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—3M bits of on-chip SRAM Code compatible with all other members of the SHARC family The ADSP-2136x processors are available ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS Summary ............................................................... 1 Dedicated Audio Components .................................... 1 Revision History ...................................................... 2 General Description ................................................. 3 SHARC Family Core Architecture ............................ 4 Family Peripheral Architecture ................................ 6 I/O Processor Features ........................................... 8 System Design ...................................................... 8 ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 GENERAL DESCRIPTION ® The ADSP-2136x SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SHARC FAMILY CORE ARCHITECTURE The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Data Register File Each processing element contains a general-purpose data regis- ter file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) files, combined ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 3. ADSP-2136x Internal Memory Space IOP Registers 0x0000 0000–0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Block 0 ROM Block 0 ROM 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 Reserved 0x0004 8000–0x0004 BFFF ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 generate either center-aligned or edge-aligned PWM wave- forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four PWM waveforms). The PWM ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 audio channels in I2S, left-justified sample pair, or right-justi- fied mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, one- half of a frame at a ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 100nF 10nF V DDINT HIGH-Z FERRITE BEAD CHIP LOCATE ALL COMPONENTS CLOSE TO A AND A VDD VSS Figure 3. Analog Power (A ) Filter Circuit VDD Target Board JTAG Emulator Connector Analog Devices’ DSP Tools product line of ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 The expert linker is fully compatible with the existing linker def- inition file (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PIN FUNCTION DESCRIPTIONS The processor’s pin definitions are listed below. Inputs identi- fied as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS and TDI). Table 6. Pin Descriptions State During ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 6. Pin Descriptions (Continued) State During and Pin Type After Reset SPICLK I/O Three-state with (pu) pull-up enabled, driven high in SPI- master boot mode SPIDS I Input only MOSI I/O (O/D) Three-state with (pu) pull-up enabled, driven ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 6. Pin Descriptions (Continued) State During and Pin Type After Reset BOOT_CFG1–0 I Input only RESETOUT O Output only RESET I/A Input only TCK I Input only TMS I/S Three-state with (pu) pull-up enabled TDI I/S Three-state with ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPECIFICATIONS Specifications are subject to change without notice. OPERATING CONDITIONS Parameter Description V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 1 V High Level Input Voltage @ V IH ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE INFORMATION The information presented in Figure 4 the package branding for the ADSP-2136x processor. For a complete listing of product availability, see Page 54. ADSP-2136x tppZ-cc vvvvvv.x n.n #yyww country_of_origin Figure 4. Typical Package Brand Table 7. Package ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 • The product of CLKIN and PLLM must never exceed f (max) in Table 11 if the input divider is enabled (INDIV = 1). The VCO frequency is calculated as follows × PLLM × f VCO ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Power-Up Sequencing The timing requirements for processor startup are given in Table 10. Note that during power-up, when the V supply comes up after leakage current of the order of DDEXT Table 10. Power-Up Sequencing Timing ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Clock Input Table 11. Clock Input Parameter Timing Requirements t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t CLKIN Rise/Fall (0 2.0 V) CKRF 4 t CCLK Period CCLK 5 t ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Reset Table 12. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin). Table 14. Core Timer Parameter Switching Characteristic t TMREXP Pulse Width WCTIM FLAG3 (TMREXP) Timer PWM_OUT Cycle Timing The following ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 6 on Page 11 for more information on flag use. Table 19. Flags Parameter Timing ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the processor is accessing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter Timing Requirements t AD7–0 Data Setup Before RD High ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 21. 16-Bit Memory Read Cycle Parameter Timing Requirements t AD15–0 Data Setup Before RD High DRS t AD15–0 Data Hold After RD High DRH Switching Characteristics t ALE Pulse Width ALEW 1 t AD15–0 Address Setup Before ALE ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the processor is accessing external memory space. Table 22. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW 1 t ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 23. 16-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW 1 t AD15–0 Address Setup Before ALE Deasserted ADAS t ALE Deasserted to Write Asserted ALERW t Write Deasserted to ALE Asserted RWALE 2 t ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync (FS) delay and frame sync setup and hold, 2) data delay and data setup and ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKIW DAI_P20–1 (SCLK) t DFSIR t t HOFSIR SFSI DAI_P20–1 (FRAME SYNC) t SDRI DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 26. Serial Ports—External Late Frame Sync Parameter Switching Characteristics 1 t Data Delay from Late External Transmit Frame Sync DDTLFSE or External Receive FS with MCE = 1, MFD = Data Enable for MCE = ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 27. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Input Data Port (IDP) The timing requirements for the IDP are given in signals are routed to the DAI_P20–1 pins using the SRU. There- fore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28. IDP ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, refer to the ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Pulse-Width Modulation Generators 1 Table 30. PWM Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP 1 Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins). PWM ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 2 Figure 30 shows the default I S-justified mode. The frame sync is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 36. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. This feature is not available on the ADSP-21363 processors. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Master The processor contains two SPI ports. The primary has dedi- cated pins and the secondary is available through the DAI. The timing provided in Table 39 and Table 40 Table 39. SPI Interface Protocol—Master Switching and Timing ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Slave Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPIDS (INPUT) t SPICHS SPICLK ( (INPUT) t SDSCO SPICLK ( (INPUT) t DSOE MISO (OUTPUT) t CPHASE = 1 SSPIDS MOSI (INPUT) MISO (OUTPUT) t DSOV CPHASE = 0 MOSI (INPUT) t SPICLS t ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 JTAG Test Access Port and Emulation Table 41. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTPUT DRIVE CURRENTS Figure 37 shows typical I-V characteristics for the output driv- ers of the processor. The curves represent the current drive capability of the output drivers as a function of output voltage ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 0.0488x - 1.5923 100 LOAD CAPACITANCE (pF) Figure 42. Typical Output Delay or Hold versus Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The processor is ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 144-LEAD LQFP_EP PIN CONFIGURATIONS The following table shows the processor’s pin names and, when applicable, their default function after reset in parentheses. Table 45. LQFP_EP Pin Assignments Pin Name Pin No. Pin Name DDINT DDINT CLK_CFG0 ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 43 shows the top view of the 144-lead LQFP_EP pin con- figuration. Figure 44 shows the bottom view of the 144-lead LQFP_EP lead configuration. LEAD 1 INDICATOR ADSP-2136x 144-LEAD LQFP_EP BOTTOM VIEW LEAD 144 LEAD 109 LEAD 1 ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 136-BALL BGA PIN CONFIGURATIONS The following table shows the processor’s ball names and, when applicable, their default function after reset in parentheses. Table 46. BGA Pin Assignments Ball Name Ball No. Ball Name CLK_CFG0 A01 CLK_CFG1 XTAL A02 GND ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 46. BGA Pin Assignments (Continued) Ball Name Ball No. Ball Name AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 KEY V DDINT GND V A DDEXT VSS Figure 45. BGA Pin Assignments (Bottom View, Summary ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE DIMENSIONS The processor is available in 136-ball BGA and 144-lead exposed pad (LQFP_EP) packages. 1.60 MAX 0.75 0.60 0.45 SEATING PLANE 1.45 1.40 0.20 1.35 0.09 7° 0.15 3.5° 0.05 0.08 0° COPLANARITY VIEW A ROTATED 90° CCW ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 1.70 MAX SURFACE-MOUNT DESIGN Table 47 is provided as an aid to PCB design. For industry stan- dard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 47. BGA Data for Use with ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 AUTOMOTIVE PRODUCTS Some ADSP-2136x models are available for automotive applica- tions with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. Table 48. Automotive Products Model Notes 2 AD21362WBBCZ1xx 2 AD21362WBSWZ1xx ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ORDERING GUIDE 1 Model Notes 3 ADSP-21362BBCZ-1AA 3 ADSP-21362BSWZ-1AA 3 ADSP-21362YSWZ-2AA ADSP-21363KBC-1AA ADSP-21363KBCZ-1AA ADSP-21363KSWZ-1AA ADSP-21363BBC-1AA ADSP-21363BBCZ-1AA ADSP-21363BSWZ-1AA 4 ADSP-21363YSWZ-2AA ADSP-21364KBC-1AA ADSP-21364KBCZ-1AA ADSP-21364KSWZ-1AA ADSP-21364BBC–1AA ADSP-21364BBCZ-1AA ADSP-21364BSWZ-1AA ADSP-21364YSWZ-2AA ADSP-21365BBCZ-1AA ADSP-21365BSWZ-1AA ADSP-21365YSWZ-2AA 3, ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev Page March 2011 ...
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06359-0-3/11(G) Rev Page March 2011 ...