ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 39

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver. This feature is not available on the
ADSP-21363 processors.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)
1
Parameter
Switching Characteristics
t
t
t
t
t
Serial clock frequency is 64 ×FS where FS = the frequency of frame sync.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Frame Sync Delay After Serial Clock
Frame Sync Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
Transmit Serial Clock Width
(DATA CHANNEL
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
A/B)
Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing
DRIVE EDGE
Rev. G | Page 39 of 56 | March 2011
t
t
HOFSI
HDTI
t
t
DFSI
DDTI
t
SCLKIW
Min
–2
–2
38
SAMPLE EDGE
Max
5
5
Unit
ns
ns
ns
ns
ns