ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 32

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Input Data Port (IDP)
The timing requirements for the IDP are given in
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 28. IDP
1
Parameter
Timing Requirements
t
t
t
t
t
t
The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Clock Rising Edge
Frame Sync Hold After Clock Rising Edge
Data Setup Before Clock Rising Edge
Data Hold After Clock Rising Edge
Clock Width
Clock Period
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
Table
Rev. G | Page 32 of 56 | March 2011
28. IDP
Figure 24. IDP Master Timing
t
IPDCLKW
t
SISFS
SAMPLE EDGE
t
SISD
t
t
SIHFS
SIHD
t
IPDCLK
Min
3
3
3
3
(t
t
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Unit
ns
ns
ns
ns
ns
ns