ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 36

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29
the left channel and low for the right channel. Data is valid on
the rising edge of serial clock. The MSB is delayed the minimum
in 24-bit output mode or the maximum in 16-bit output mode
from a frame sync transition, so that when there are 64 serial
clock periods per frame sync period, the LSB of the data is right-
justified to the next frame sync transition.
Table 33. S/PDIF Transmitter Right-Justified Mode
Parameter
Timing Requirement
t
RJD
shows the right-justified mode. Frame sync is high for
2
S, or right justified with word widths of 16-, 18-,
DAI_P20–1
DAI_P20–1
DAI_P20–1
SDATA
SCLK
FS
FS to MSB Delay in Right-Justified Mode
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
LSB
t
RJD
Rev. G | Page 36 of 56 | March 2011
Figure 29. Right-Justified Mode
MSB
LEFT/RIGHT CHANNEL
MSB–1
MSB–2
Nominal
16
14
12
8
LSB+2
LSB+1
LSB
Unit
SCLK
SCLK
SCLK
SCLK