ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 35

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and should
meet setup and hold times with regard to the serial clock on the
output port. The serial data output has a hold time and delay
Table 32. SRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be
SRCSFS
SRCHFS
SRCTDD
SRCTDH
either CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
t
SRCTDH
Rev. G | Page 35 of 56 | March 2011
Figure 28. SRC Serial Output Port Timing
t
SRCTDD
t
SRCCLKW
t
SRCSFS
SAMPLE EDGE
specification with regard to serial clock. Note that the serial
clock rising edge is the sampling edge and the falling edge is the
drive edge.
Min
3
3
2
t
SRCHFS
K and B Grade
t
SRCCLK
Max
10.5
Max
12.5
Y Grade
Unit
ns
ns
ns
ns