LFM34INTPU1A Freescale Semiconductor, LFM34INTPU1A Datasheet

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... The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. © Freescale Semiconductor, Inc., 2008, 2010. All rights reserved. Document Number: MPC5534 Rev. 5, Oct 2010 Contents 1 Overview ...

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... SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer sub-block (IMUX) provides multiplexing of eQADC trigger sources and external interrupt signal multiplexing. 2 MPC5534 Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor ...

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... Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 68 MHz parts allow for 66 MHz system clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM. Freescale Semiconductor M PC 5534 ...

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... DDA DD – V –0.3 5.5 RL – V –5.5 5.5 DDA – V –0.3 0.3 SSA – V –V V DDA DDA DDEH – V –0.3 0 Electrical Specifications, Spec 43a. – V –0.1 0.1 SS – V –0.1 0.1 SS –2 2 MAXD –3 3 MAXA T T 150 –55.0 150.0 STG Freescale Semiconductor Unit ...

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... Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Freescale Semiconductor 11 and ...

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... Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device can be obtained from the equation: J  MPC5534 Microcontroller Data Sheet, Rev. 5 C/W) 2 Freescale Semiconductor ...

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... T + ( where thermocouple temperature on top of the package ( T  = thermal characterization parameter ( power dissipation in the package (W) D Freescale Semiconductor  C/W) per JESD51-8 CA o C/W) o C/W) . For example, change the air flow around the device,  determine the junction temperature by measuring the ...

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... Table 4. EMI Testing Specifications Minimum 0.15 — — operating voltages — DDE — — — MPC5534 Microcontroller Data Sheet, Rev. 5 Section 2, “Ordering 1 Typical Maximum Unit — 1000 MHz — f MHz MAX 1.5 — V 3.3 — V 5.0 — — 14 dBuV — Freescale Semiconductor ...

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... Tj: RCCTL Voltage differential during power up such that can lag DD33 DDSYN DDEH6 V and V minimums respectively. POR33 POR5 Freescale Semiconductor 1, 2 Table 5. ESD Ratings Symbol R1 C — — — ) and RC and POR electrical specifications: and POR Electrical Specifications RC Characteristic Negated (ramp up) ...

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... DD = 2.2 V. VRCCTL Electrical Specification. DD  the RESET power supplies is required and during power up, V DDSYN stage turn-on to operate RC leads or lags RC33 to rise until the 1.5 V POR DD Freescale Semiconductor Units 50 V/ms — — — — 500 — DC Electrical I ). VRCCTL must RC33 ...

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... V To avoid this condition, minimize the ramp time of the V required to enable the external circuitry connected to the device outputs. Freescale Semiconductor have no delta requirement to each other, because the bypass DDSYN to operate within specification. ...

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... RC33 RC33 MPC5534 Microcontroller Data Sheet, Rev. 5 DD33 or RESET power pin (V DDEH6 can lag V or the RESET power DDSYN lag specification DD33 power supply and the RESET DDSYN V and RESET Power DDSYN V DD Grounded) grounded decreases to less than DD Freescale Semiconductor ) by power DD ...

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... Load capacitance (fast I/O) DSC (SIU_PCR[8:9]) = 0b00 = 0b01 = 0b10 = 0b11 24 Input capacitance (digital pins) 25 Input capacitance (analog pins) 26 Input capacitance: (Shared digital and analog pins AN[12]_MA[0]_SDS, AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK) Freescale Semiconductor 1 = –2.0 mA) MPC5534 Microcontroller Data Sheet, Rev. 5 Electrical Characteristics = Symbol Min Max ...

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... DDSYN I — 20.0 DD_A I — 1.0 REF I — 25 — Refer to DD1 I — footnote DD2 I — DD3 I — DD4 I — DD5 I — DD6 I — DD7 I — DD8 I — DD9 Freescale Semiconductor Unit A A A A A A A A  ...

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... Average current measured on Automotive benchmark. 9 Peak currents can be higher on specialized code. 10 High use current measured while running optimized SPE assembly code with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Freescale Semiconductor ground ...

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... The and 3.6 V and V = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. DDE DDEH 125 C. Applies to pad types: pad_a and pad_ae – must be < 0.1 V. SSA0 SSA1 MPC5534 Microcontroller Data Sheet, Rev Freescale Semiconductor ...

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... Freescale Semiconductor worst-case specification to estimate values at STBY Table 9. Istby vs. Junction Tem Tem p (C) Figure 3. I Worst-case Specifications STBY MPC5534 Microcontroller Data Sheet, Rev. 5 Electrical Characteristics   ...

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... Freescale Semiconductor ...

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... These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped. Freescale Semiconductor Current Specifications supply dependents on the usage of the pins on all I/O segments. The DD33 ...

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... DDE5 0.8 3 — 1.5 — 1.5 Refer to crystal Refer to crystal specification specification (2  – S_EXTAL — 9 – C PCB_EXTAL (2  – S_XTAL — 9 – C PCB_XTAL — 750 – –4.0 4.0 –2.0 2.0 Freescale Semiconductor Unit MHz MHz ns kHz MHz  SYS % f SYS ...

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... Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the ICO output and then divide-by-two the RFD to provide the 40 MHz clock. 18 Maximum value for dual controller (1:1) mode is (f Freescale Semiconductor = 3.0–3 0 ...

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... The ADCLK  V due to the presence of the sample RL SSA 9. DC Electrical Specifications, spec 35a) can Freescale Semiconductor Unit MHz ADCLK cycles  Counts Counts Counts Counts Counts Counts mA Counts Counts ...

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... Data retention 2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–100,000 P/E cycles 1 Typical endurance is evaluated at 25 information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for Nonvolatile Memory. Freescale Semiconductor Symbol 4 T dwprogram T pprogram T 16kpperase ...

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... V) DDE 4, 5 Rise / Fall Load Drive (ns) (pF 200 200 200 50 260 200 Freescale Semiconductor 2 BFEN 0b0 0b1 0b0 0b1 0b0 0b1 0b0 0b1 0b0 ...

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... The output delay and rise and fall are measured to 20% or 80% of the respective signal. 5 This parameter is guaranteed by characterization rather than 100% tested. Table 18. Derated Pad AC Specifications (V Spec Pad 1 Slow high voltage (SH) 2 Medium high voltage (MH) Freescale Semiconductor = 5 DDEH SRC / DSC Out Delay (binary) (ns ...

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... Figure 4. Pad Output Delay Characteristic MPC5534 Microcontroller Data Sheet, Rev 3.3 V) (continued) DDE Rise / Fall Load Drive (ns) 2.4 2.2 2.1 2.1 — 7500 — 9500 = 3.0–3.6 V; and Symbol Min. Max — RPW t 2 — GPW Freescale Semiconductor (pF 2 Unit t CYC t CYC ...

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... TMS, TDI data hold time 6 TCK low to TDO data valid 7 TCK low to TDO data invalid 8 TCK low to TDO high impedance 9 JCOMP assertion time 10 JCOMP setup time to TCK low 11 TCK falling-edge to output valid Freescale Semiconductor Characteristic =  2) DDE MPC5534 Microcontroller Data Sheet, Rev. 5 Electrical Characteristics ...

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... These specifications apply to JTAG boundary scan only. JTAG timing specified at: V Refer to Table 21 for Nexus specifications. TCK Figure 6. JTAG Test Clock Input Timing MPC5534 Microcontroller Data Sheet, Rev (continued) Symbol Min. Max. t — 50 BSDVZ t — 50 BSDHZ t 50 — BSDST t 50 — BSDHT = 3.0–3.6 V and DDE Freescale Semiconductor Unit ...

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... TCK TMS, TDI TDO TCK JCOMP Freescale Semiconductor Figure 7. JTAG Test Access Port Timing 9 Figure 8. JTAG JCOMP Timing MPC5534 Microcontroller Data Sheet, Rev. 5 Electrical Characteristics ...

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... Electrical Characteristics TCK 11 Output signals 12 Output signals Input signals Figure 9. JTAG Boundary Scan Timing MPC5534 Microcontroller Data Sheet, Rev Freescale Semiconductor ...

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... MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs. 4 Limit the maximum frequency to approximately 16 MHz (V specification for JOV JCYC 5 The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly. MCKO MDO MSEO EVTO Freescale Semiconductor Table 21. Nexus Debug Port Timing 1.35–1. and with DSC = 0b10 2.25– ...

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... Electrical Characteristics TCK TMS, TDI TDO Figure 11. Nexus TDI, TMS, TDO Timing MPC5534 Microcontroller Data Sheet, Rev Freescale Semiconductor ...

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... CLKOUT positive edge to t COV output signal valid (output delay) External bus interface CS[0:3] ADDR[8:31 DATA[0:15] RD_WR BDIP WE/BE[0: Freescale Semiconductor Table 22. External Bus Operation Timing External Bus Frequency 20 MHz 33 MHz Min. Max Min. Max 24.4 — 17.5 — C 45% 55% 45% ...

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... MPC5534 Microcontroller Data Sheet, Rev (continued) 3 Notes 40 MHz Unit Min. Max  6 11.0 ns EBTS = 0 — 12.0 EBTS = 1 Output valid time selectable via SIU_ECCR [EBTS] bit. 10.0 — ns 11.0 — ns 1.0 — ns 1.0 — and with DSC = 0b10. H Freescale Semiconductor ...

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... Available on the 324 package only; not available on the 208 package. 6 EBTS = 0 timings are tested and valid at V Vol_f CLKOUT Freescale Semiconductor and Table 18 (different values for 1.8 V and 3.3 V). = 2.25–3.6 V only; EBTS = 1 timings are tested and valid at V DDE Voh_f ...

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... Electrical Characteristics CLKOUT 5 Output 2 V DDE bus 5 Output 2 V DDE signal Output signal Figure 13. Synchronous Output Timing MPC5534 Microcontroller Data Sheet, Rev. 5 2 DDE 5 2 V DDE 5 6 2 V DDE Freescale Semiconductor ...

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... IRQ pulse-width high 2 3 IRQ edge-to-edge time 1 IRQ timing specified at 3.0–5.25 V and T DDEH 2 Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both. Freescale Semiconductor 2 V DDE 7 2 V DDE 7 Figure 14. Synchronous Input Timing Table 23. External Interrupt Timing ...

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... TCRCLK Figure 15. External Interrupt Timing 1 Table 24. eTPU Timing = Figure 16. eTPU Timing MPC5534 Microcontroller Data Sheet, Rev. 5 Symbol Min. Max t 4 — ICPW — OCPW 2 Freescale Semiconductor Unit t CYC t CYC ...

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... After SCK delay SCK duty cycle 4 Slave access time 5 (SS active to SOUT driven) Slave SOUT disable time 6 (SS inactive to SOUT Hi-Z, or invalid) 7 PCSx to PCSS time Freescale Semiconductor Table 25. eMIOS Timing Characteristic = Figure 17. eMIOS Timing 1, 2 Table 26. DSPI Timing 40 MHz Symbol Min ...

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... DDEH A L Freescale Semiconductor Unit and H ...

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... SCK output (CPOL=1) SIN SOUT Figure 18. DSPI Classic SPI Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 19. DSPI Classic SPI Timing—Master, CPHA = 1 Freescale Semiconductor Last data First data Data 12 11 First data Data Last data ...

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... SCK input (CPOL=1) SOUT SIN Figure 21. DSPI Classic SPI Timing—Slave, CPHA = First data Data Last data 9 10 Data Last data First data 11 5 Data First data 9 10 Data First data MPC5534 Microcontroller Data Sheet, Rev Last data Last data Freescale Semiconductor ...

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... SIN SOUT Figure 22. DSPI Modified Transfer Format Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = 1 Freescale Semiconductor First data Last data Data 12 11 First data Last data Data ...

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... Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA = 1 PCSS PCSx First data Data Last data 10 9 Data First data Last data 11 5 First data Data 9 10 First data Data 7 Figure 26. DSPI PCS Strobe (PCSS) Timing MPC5534 Microcontroller Data Sheet, Rev Last data Last data 8 Freescale Semiconductor ...

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... FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number. FCK SDS SDO External device data sample at FCK falling-edge SDI EQADC data sample at FCK rising-edge Freescale Semiconductor Symbol Minimum FCK  6 ...

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... BOOT RXDB CFG0 CFG1 EMIOS VRC PLL VDD33 VSS EXTAL 21 CTL CFG1 EMIOS CNTXA VDD VSS VRC33 22 EMIOS CNRXA CNRXB VDD VSS 23 EMIOS ENG CNTXB VDDE5 VDD 20 CLK Freescale Semiconductor 16 VSS A VDD B TCK C TEST VSS M SYN N XTAL P VDD R SYN VSS T 16 ...

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... VDD ADDR DATA GPIO VDDE2 VDDE2 AA VSS VDD 29 1 DATA DATA DATA DATA AB VSS VDD VDDE2 Freescale Semiconductor NOTE AN1 AN5 VRH VRL AN27 AN28 REF AN0 AN4 AN23 AN26 AN31 BYPC AN21 AN3 AN7 AN22 AN25 AN30 AN9 AN10 AN18 ...

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... Mechanicals 4.3 MPC5534 208-Pin Package Dimensions The package drawings of the MPC5534 208-pin MAP BGA are shown in 48 Figure 30. MPC5534 208-Pin Package MPC5534 Microcontroller Data Sheet, Rev. 5 Figure 30. Freescale Semiconductor ...

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... Figure 30. MPC5534 208 MAP BGA Package (continued) Freescale Semiconductor MPC5534 Microcontroller Data Sheet, Rev. 5 Mechanicals 49 ...

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... Mechanicals 4.4 MPC5534 324-Pin Package Dimensions The package drawings of the MPC5534 324-pin TEPBGA package are shown in 50 Figure 31. MPC5534 324 TEPBGA Package MPC5534 Microcontroller Data Sheet, Rev. 5 Figure 31. Freescale Semiconductor ...

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... Figure 31. MPC5534 324 TEPBGA Package (continued) Freescale Semiconductor MPC5534 Microcontroller Data Sheet, Rev. 5 Mechanicals 51 ...

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... Last paragraph: Changed the first sentence FROM . . . the voltage on the pins goes to high-impedance until . . . TO. . .the pins high-impedance state until . . . 5.2 Changes Between Revisions 3.0 and 4.0 The following table lists the substantive text changes made to paragraphs. 52 Description of Changes NOTE MPC5534 Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor ...

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... V To avoid this condition, minimize the ramp time of the V enable the external circuitry connected to the device outputs.’ Section 3.7.3, “Power-Down Sequence (VRC33 Freescale Semiconductor Description of Changes Table 1: ‘Unless noted in this data sheet, all specifications apply Grounded),” ...

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... RC33 DDSYN MPC5534 Microcontroller Data Sheet, Rev the highest ambient L powered I/O pads” that reads: ‘Internal DDE supplies, if the DDE is within the operating voltage DDE to V differential voltage.’ SSA to V differential voltage.’ DDA Freescale Semiconductor ...

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... Spec 28: Changed 82 MHz to f • Footnote 9: Changed from ‘Preliminary. Final specification pending characterization.’ to illustration of the I DD_STBY Freescale Semiconductor Description of Changes DC Electrical Specifications. On power down, assert RESET before any power supplies DC Electrical Specifications. On power down, assert RESET before any power supplies Min 0 ...

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... MAX 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’ MAX = – the table title MPC5534 Microcontroller Data Sheet, Rev. 5 – T )’ to the table title typical supply voltage using a Freescale Semiconductor ...

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... Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).’ Freescale Semiconductor Description of Changes Table 18, Derated Pad AC Specifications: The changes are identical in the tables MHz’ ...

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... V’ and ‘V and V DD DD33 DDSYN Figure 29 MPC5534 324 Package: Deleted the version number and date. Figure 31 MPC5534 324 Package Dimensions: MPC5534 Microcontroller Data Sheet, Rev. 5 and V = 3.0–3.6 V’ and DD33 DDSYN = 3.0–3 3.0–3.6V.’ Freescale Semiconductor ...

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... Freescale Semiconductor MPC5534 Microcontroller Data Sheet, Rev. 5 Revision History for the MPC5534 Data Sheet 59 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...