LFM34INTPU1A Freescale Semiconductor, LFM34INTPU1A Datasheet - Page 39

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LFM34INTPU1A

Manufacturer Part Number
LFM34INTPU1A
Description
ADAPTER MPC5534 324-BGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of LFM34INTPU1A

Module/board Type
Adapter Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
-
3.13.7
1
2
3.13.8
Freescale Semiconductor
Spec
Spec
eMIOS timing specified at: V
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).
1
2
3
4
5
6
7
1
2
SCK cycle time
PCS to SCK delay
After SCK delay
SCK duty cycle
Slave access time
(SS active to SOUT driven)
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or
invalid)
PCSx to PCSS time
eMIOS input pulse width
eMIOS output pulse width
eMIOS Timing
DSPI Timing
Characteristic
eMIOS
output
eMIOS input
3, 4
6
5
DDEH
= 3.0–5.25 V and T
Characteristic
MPC5534 Microcontroller Data Sheet, Rev. 5
Symbol
t
t
t
t
t
PCSC
t
SCK
CSC
ASC
SDC
DIS
t
A
Table 26. DSPI Timing
Table 25. eMIOS Timing
Figure 17. eMIOS Timing
(t
48.8 ns
SCK
– 2 ns
Min.
A
46
45
4
= T
 2)
40 MHz
L
to T
(t
5.8 ms
SCK
+ 2 ns
H
Max
25
25
.
 2)
1
1, 2
(t
28.4 ns
1
SCK
2
– 2 ns
Min.
26
25
4
 2)
66 MHz
Symbol
t
t
MOPW
(t
MIPW
3.5 ms
SCK
+ 2 ns
Max
25
25
 2)
(t
24.4 ns
Electrical Characteristics
Min.
SCK
1
– 2 ns
Min.
4
22
21
2
4
 2)
80 MHz
Max.
(t
2.9 ms
SCK
+ 2 ns
Max
25
25
 2)
t
t
Unit
CYC
CYC
Unit
ns
ns
ns
ns
ns
ns
39

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