LFM34INTPU1A Freescale Semiconductor, LFM34INTPU1A Datasheet - Page 45

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LFM34INTPU1A

Manufacturer Part Number
LFM34INTPU1A
Description
ADAPTER MPC5534 324-BGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of LFM34INTPU1A

Module/board Type
Adapter Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
-
3.13.9
Freescale Semiconductor
1
2
Spec
SS timing specified at V
varies depending on track delays, master pad delays, and slave pad delays.
FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
2
3
4
5
6
7
8
External device data sample at
FCK period (t
Clock (FCK) high time
Clock (FCK) low time
SDS lead / lag time
SDO lead / lag time
EQADC data setup time (inputs)
EQADC data hold time (inputs)
EQADC data sample at
eQADC SSI Timing
FCK falling-edge
FCK rising-edge
FCK
Rating
DDEH
= 1
SDO
SDS
FCK
SDI
= 3.0–5.25 V, T
f
FCK
Table 27. EQADC SSI Timing Characteristics
)
1, 2
MPC5534 Microcontroller Data Sheet, Rev. 5
Figure 27. EQADC SSI Timing
A
= T
L
Symbol
t
t
t
t
t
t
SDO_LL
to T
SDS_LL
EQ_SU
EQ_HO
5
FCKHT
6
FCKLT
t
FCK
3
H
, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
2
1st (MSB)
4
t
t
SYS_CLK
SYS_CLK
7
Minimum
1st (MSB) 2nd
–7.5
–7.5
22
2
1
8
 6.5
 6.5
2nd
Typical
25th
25th
9  (t
8  (t
26th
Maximum
Electrical Characteristics
SYS_CLK
SYS_CLK
+7.5
+7.5
17
4
5
 6.5)
 6.5)
26th
t
SYS_CLK
Unit
ns
ns
ns
ns
ns
ns
45

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