LFM34INTPU1A Freescale Semiconductor, LFM34INTPU1A Datasheet - Page 57

• Manufacturer Part Number: LFM34INTPU1A
• Description: ADAPTER MPC5534 324-BGA
• Manufacturer: Freescale Semiconductor

Specifications of LFM34INTPU1A

• Module/board Type: Adapter Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

Freescale Semiconductor
Table
Table
Table
Table
Table
Table
Table 24,
Location
17, Pad AC Specifications, and
19, Reset and Configuration Pin Timing: Footnote 1, deleted ‘F
20, JTAG Pin AC Electrical Characteristics:
21, Nexus Debug Port Timing.
22, Bus Operation Timing:
23, External Interrupt Timing:
eTPU Timing
Changed Spec 12, TCK Low to TDO Data Valid: Changed ‘VDDE = 3.0 to 3.6 volts’ maximum value in column 4
from 9 to 10. Now reads ‘V
•
• Footnote 1, deleted ‘F
• Footnote 2, changed from ‘tested’ to ‘(not tested).’
• Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,
• Changed from ‘ Add a maximum of one system clock to the output delay to get the output delay with respect to
• Footnote 4: changed ‘Delay’ to ‘The output delay.’
• Footnote 5: deleted ‘before qualification.’
• Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This
• Footnote 1, deleted: ‘, and CL = 30 pF with DSC = 0b10, SRC = 0b11’
• Footnote 1, changed ‘functional’ to ‘Nexus.’
• External Bus Frequency: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is
• Spec 1: Changed the system frequency columns from 40, 56, and 66 MHz to 20, 33, and 40 MHz. Changed the
• Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing
• Specs 5 and 6: Changed the following calibration signals: CAL_ADDR[8:30] to CAL_ADDR[10:30], and
• Specs 7 and 8: Changed the following calibration signals: CAL_ADDR[8:30] to CAL_ADDR[10:30]. Deleted TEA.
• Footnote 1: Changed ‘V
• Footnote 1: Deleted ‘F
• Deleted second figure after table ‘External Interrupt Setup Timing.’
• Footnote 1: Changed ‘V
• Footnote 1: Deleted ‘F
• Deleted second figure, ‘eTPU Input/Output Timing’ after this table.
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
Table
the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system
clock to the output delay.’
parameter is supplied for reference and is guaranteed by design and tested.’
the maximum speed allowed including frequency modulation (FM). 42 MHz parts allow for 40 MHz system clock
+ 2% FM; 68 MHz parts allow for 66 MHz system clock + 2% FM, and 82 MHz parts allow for
80 MHz system clock + 2% FM.
values in Min. columns: 20 MHz from 25 to 24.4; 33 MHz from 17.9 to 17.5, and 40 MHz from 15.2 to 14.9.
values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
CAL_WE/BE[0:1] to CAL_WE[0:1]. Deleted TEA.
BDIP, OE, RD_WR, and WE/BE[0:1]. CAL_CS[0, 2:3], CAL_OE, CAL_RD_WR, and CAL_WE/BE[0:1].
‘ and CL = 200 pF with SRC = 0b11.’
‘and CL = 200 pF with SRC = 0b11.’
eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Table 30. Table and Figure Changes Between Rev. 3.0 and 4.0 (continued)
17, Pad AC Specifications only: Footnote 1, changed ‘V
SYS
SYS
SYS
Table
DDEH
DDEH
DDE
MPC5534 Microcontroller Data Sheet, Rev. 5
= 80 MHz’
= 80 MHz.’,‘V
= 80 MHz.’, ‘V
18, Derated Pad AC Specifications: The changes are identical in the tables.
= 3.0–3.6 V’ with a max value of 10.
= 3.0–5.5;’ to ‘V
= 3.0–5.5;’ to ‘V
DD
DD
Description of Changes
= 1.35–1.65 V’, ‘V
= 1.35–1.65 V’, ‘V
DDEH
DDEH
= 3.0–5.25;’
= 3.0–5.25;’
SYS
= 80 MHz.’
DD33
DDEH
DD33
Revision History for the MPC5534 Data Sheet
and V
and V
= 4.5–5.5;’ to ‘V
DDSYN
DDSYN
= 3.0–3.6 V.’ and
= 3.0–3.6’ and
DDEH
= 4.5–5.25;’
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