ADV212-HD-EB Analog Devices Inc, ADV212-HD-EB Datasheet - Page 12

• Manufacturer Part Number: ADV212-HD-EB
• Description: BOARD EVALUATION FOR ADV212-HD
• Manufacturer: Analog Devices Inc

Specifications of ADV212-HD-EB

• Main Purpose: Video, Video Processing
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADV212-HD
• Primary Attributes: 1080i and 720p SDI Compatible, 32/64-bit, 33/66 MHz PCI Card
• Secondary Attributes: GUI, JPEG2000 Video Codec
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV212
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
DREQ Pulse Width
WE to DREQ Deassert (DR × PULS = 0)
DACK to WE Setup
Data Setup
Data Hold
WE Assert Pulse Width
WE Deassert Pulse Width
WE Deassert to Next DREQ
WE Deassert to DACK Deassert
1
2
Applies to assigned DMA channel, if EDMOD0/EDMOD1[14:11] is programmed to a nonzero value.
For a definition of JCLK, see Figure 32.
HDATA
HDATA
HDATA
DREQ
DACK
DREQ
DACK
WEFB
DREQ
DACK
1
WE
WE
DREQ
Figure 13. Burst Write Cycle for DREQ /DMA Mode for Assigned DMA Channel
Figure 14. Burst Write Cycle for DREQ /DMA Mode for Assigned DMA Channel
t
t
t
PULSE
t
t
t
SU
SU
t
SU
t
DACK
DACK
DACK
DREQ
DREQ
(EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000)
0
0
0
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
t
t
t
HD
HD
HD
SU
SU
SU
RTN
RTN
Figure 15. Burst Write Cycle for Fly-By DMA Mode
1
1
1
WE
WE
WE
Mnemonic
DREQ
t
t
t
t
WE
WE
t
t
DREQ RTN
DACK SU
SU
HD
DREQ WAIT
WE_DACK
LOW
LOW
LOW
Rev. B | Page 12 of 44
LOW
HIGH
PULSE
13
13
13
WE
WE
WE
HIGH
HIGH
HIGH
Min
1 JCLK
2.5 JCLK
0
2.5
2
1.5 JCLK
1.5 JCLK
2.5 JCLK
0
14
14
14
t
WE_DACK
t
t
2
WE_DACK
WE_DACK
2
2
2
2
15
15
15
Typ
t
t
DREQ
t
Max
15 JCLK
3.5 × JCLK + 7.5
4.5 × JCLK + 9.0
DREQ
DREQ
WAIT
WAIT
WAIT
2
2
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns