ADV212-HD-EB Analog Devices Inc, ADV212-HD-EB Datasheet - Page 6

BOARD EVALUATION FOR ADV212-HD

ADV212-HD-EB

Manufacturer Part Number
ADV212-HD-EB
Description
BOARD EVALUATION FOR ADV212-HD
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV212-HD-EB

Main Purpose
Video, Video Processing
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADV212-HD
Primary Attributes
1080i and 720p SDI Compatible, 32/64-bit, 33/66 MHz PCI Card
Secondary Attributes
GUI, JPEG2000 Video Codec
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
ADV212
NORMAL HOST MODE—WRITE OPERATION
Table 4.
Parameter
WE to ACK, Direct Registers and FIFO Accesses
WE to ACK, Indirect Registers
Data Setup
Data Hold
Address Setup
Address Hold
CS to WE Setup
CS Hold
Write Inactive Pulse Width (Minimum Time Until Next WE Pulse)
Write Active Pulse Width
Write Cycle Time
1
For a definition of JCLK, see Figure 32.
HDATA
ADDR
ACK
WE
CS
t
t
SC
SA
t
ACK
Figure 3. Normal Host Mode—Write Operation
t
WL
t
SD
VALID
Rev. B | Page 6 of 44
t
t
HC
HD
t
HA
t
WCYC
Mnemonic
t
t
t
t
t
t
t
t
t
t
t
t
ACK
ACK
SD
HD
SA
HA
SC
HC
WH
WL
WCYC
WH
(direct)
(indirect)
Min
5
5
3.0
1.5
2
2
0
0
2.5 JCLK
2.5 JCLK
5 JCLK
1
1
1
Typ
Max
1.5 × JCLK + 7.0
2.5 × JCLK + 7.0
1
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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