ADV212-HD-EB Analog Devices Inc, ADV212-HD-EB Datasheet - Page 7

• Manufacturer Part Number: ADV212-HD-EB
• Description: BOARD EVALUATION FOR ADV212-HD
• Manufacturer: Analog Devices Inc

Specifications of ADV212-HD-EB

• Main Purpose: Video, Video Processing
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADV212-HD
• Primary Attributes: 1080i and 720p SDI Compatible, 32/64-bit, 33/66 MHz PCI Card
• Secondary Attributes: GUI, JPEG2000 Video Codec
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

NORMAL HOST MODE—READ OPERATION
Table 5.
Parameter
RD to ACK, Direct Registers and FIFO Accesses
RD to ACK, Indirect Registers
Read Access Time, Direct Registers
Read Access Time, Indirect Registers
Data Hold
CS to RD Setup
Address Setup
CS Hold
Address Hold
Read Inactive Pulse Width
Read Active Pulse Width
Read Cycle Time, Direct Registers
1
2
Timing relationship between ACK falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to RD rising transition.
A minimum of three JCLK cycles is recommended between ACK assert and RD deassert.
For a definition of JCLK, see Figure 32.
HDATA
ADDR
ACK
CS
RD
t
t
SA
SC
t
ACK
t
Figure 4. Normal Host Mode—Read Operation
RL
t
DRD
VALID
Rev. B | Page 7 of 44
t
Mnemonic
t
t
t
t
t
t
t
t
t
t
t
t
HC
ACK
ACK
DRD
DRD
HZRD
SC
SA
HC
HA
RH
RL
RCYC
t
HA
t
(direct)
(indirect)
(direct)
(indirect)
RCYC
t
HZRD
t
RH
1
1
Min
5
10.5 JCLK
5
10.5 JCLK
2
0
2
0
2
2.5 JCLK
2.5 JCLK
5.0 JCLK
2
2
2
2
2
Typ
Max
1.5 × JCLK + 7.0
15.5 × JCLK + 7.0
1.5 × JCLK + 7.0
15.5 × JCLK + 7.0
8.5
2
2
2
2
ADV212
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns