SI3230PPQX-EVB Silicon Laboratories Inc, SI3230PPQX-EVB Datasheet - Page 26

• Manufacturer Part Number: SI3230PPQX-EVB
• Description: BOARD EVAL W/DISCRETE INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3230PPQX-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3230
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3230
2.2.5. DC-DC Converter Enhancements
There are two enhancements to the dc-dc converter.
The first is a multi-threshold error control algorithm that
enables the dc-dc converter to adjust more quickly to
voltage changes. This option is enabled by setting
DCSU = 1 (direct Register 108, bit 5). The second
enhancement is an audio band filter that removes audio
band noise from the dc-dc converter control loop. This
option
Register 108, bit 1).
2.2.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires
voltages well above those used in the active mode. The
voltage to be generated and regulated by the dc-dc
converter during a ringing burst is set using the VBATH
register (direct Register 74). VBATH can be set between
0 and –94.5 V in 1.5 V steps. To avoid clipping the
ringing signal, V
amplitude. At the end of each ringing burst the dc-dc
converter adjusts back to active state regulation as
described above.
26
Counter
Modulo
16-Bit
is
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
OATn
8 kHz
Clock
OITn
enabled
BATH
OATnE
OITnE
must be set larger than the ringing
Expire
Expire
by
OAT
OIT
OnE
setting
Figure 11. Simplified Tone Generator Diagram
Cross
Logic
Zero
Logic
Logic
INT
INT
DCFIL = 1
OZn
Zero Cross
OSSn
Logic
OnAE
Load
OnAP
OnIE
OnIP
Preliminary Rev. 0.96
REL*
(direct
Register
Enable
Load
Resonance
2.3. Tone Generation
Two digital tone generators are provided in the ProSLIC.
They allow the generation of a wide variety of single or
dual tone frequency and amplitude combinations and
spare the user the effort of generating the required
POTS signaling tones on the PCM highway. DTMF, FSK
(caller ID), call progress, and other tones can all be
generated on-chip.
2.3.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 11. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected to give the user flexibility in creating audio
signals. Control and status register bits are placed in the
figure to indicate their association with the tone
generator architecture. These registers are described in
more detail in Table 25.
Two-Pole
Oscillator
8 kHz
Clock
OSCnX
OSCnY
OSCn
Routing
Signal
OnSO
to TX Path
to RX Path