SI3230PPQX-EVB Silicon Laboratories Inc, SI3230PPQX-EVB Datasheet - Page 31

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SI3230PPQX-EVB

Manufacturer Part Number
SI3230PPQX-EVB
Description
BOARD EVAL W/DISCRETE INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet

Specifications of SI3230PPQX-EVB

Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3230
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.
where T = ringing period, and CF = desired crest factor.
For example, to generate a 71 V
signal, the equations are as follows:
For a crest factor of 1.3 and a period of 0.05 seconds
(20 Hz), the rise time requirement is 0.0153 seconds.
In addition, the user must select the trapezoidal ringing
waveform by writing TSWS = 1 in direct Register 34.
2.4.4. Ringing DC voltage Offset
A dc offset can be added to the ac ringing waveform by
defining
Register 19). The offset, V
signal when RVO is set to 1 (direct Register 34, bit 1).
The value of ROFF is calculated as follows:
2.4.5. Linefeed Considerations During Ringing
Care must be taken to keep the generated ringing signal
within the ringing voltage rails (GNDA and V
maintains proper biasing of the external bipolar
transistors. If the ringing signal nears the rails, a
distorted ringing signal and excessive power dissipation
in the external transistors will result.
To prevent this invalid operation, set the VBATH value
(direct Register 74) to a value higher than the maximum
peak ringing voltage. The discussion below outlines the
considerations and equations that govern the selection
of the VBATH setting for a particular desired peak
ringing voltage.
First, the required amount of ringing overhead voltage,
V
current through the load, I
gain of Q5 and Q6, and a reasonable voltage required
to keep Q5 and Q6 out of saturation. For ringing signals
up to V
However, to determine V
OVR
RNGY 20 Hz
, is calculated based on the maximum value of
RNGX 71 V
PK
(
the
RCO 20 Hz , 1.3 crest factor
(
=
= 87 V, V
------------------------------------- -
0.0153 8000
)
offset
(
2 24235
ROFF
PK
t
=
×
RISE
1
-- -
2
)
×
×
=
OVR
--------------- -
20 Hz
=
71
----- -
96
voltage
=
OVR
3
-- - T 1
4
1
LOAD,PK
V
----------------- -
ROFF
×
= 7.5 V is a safe value.
=
ROFF
2
96
for a specific case, use the
×
15
396
8000
, is added to the ringing
=
---------- -
CF
×
=
24235
, the minimum current
1
in
2
2
018Ch
15
=
PK
200
ROFF
, 20 Hz ringing
)
=
5EABh
=
C8h
Preliminary Rev. 0.96
(indirect
BAT
) to
equations below.
where:
N
I
(max value = 2 mA), and
V
It is good practice to provide a buffer of a few more
milliamperes for I
leakages, etc. The total I
smaller than 80 mA.
where
transistors Q5 and Q6.
The minimum value for VBATH is therefore given by the
following:
The ProSLIC is designed to create a fully balanced
ringing waveform, meaning that the TIP and RING
common mode voltage, (V
voltage
automatically set to the following:
VCMR is an indirect register which provides the
headroom by the ringing waveform with respect to the
VBATH rail. The value is set as a 4-bit setting in indirect
Register 40 with an LSB voltage of 1.5 V/LSB.
Register 40 should be set with the calculated V
provide voltage headroom during ringing.
Silicon revisions C and higher support the option to
briefly increase the maximum differential current limit
between the voltage transition of TIP and RING from
ringing to a dc linefeed state. This mode is enabled by
setting ILIMEN = 1 (direct Register 108, bit 7).
2.4.6. Ring Trip Detection
A ring trip event signals that the terminal equipment has
gone off-hook during the ringing state. The ProSLIC
performs ring trip detection digitally using its on-chip
monitor A/D converter. The functional blocks required to
implement ring trip detection is shown in Figure 14. The
primary input to the system is the Loop Current Sense
value provided by the current monitoring circuitry and
reported in direct Register 79. LCS data is processed by
the input signal processor when the ProSLIC is in the
OS
AC,PK
REN
is the offset current flowing in the line driver circuit
I
LOAD,PK
is the ringing REN load (max value = 5),
V
= amplitude of the ac ringing waveform.
β
OVR
is
VBATH
is the minimum expected current gain of
VCM _ RING
=
=
referred
I
V
------------------ -
R
LOAD,PK
AC,PK
LOAD
LOAD,PK
=
V
AC,PK
+
=
×
to
I
OS
β
------------ -
VBATH VCMR
--------------------------------------------- -
TIP
to account for possible line
+
β
+
LOAD,PK
=
as
1
V
×
ROFF
+ V
V
AC,PK
(
80.6 Ω
2
VCM_RING
RING
+
current should be
V
×
)/2, is fixed. This
OVR
----------------- -
6.9 k Ω
+
N
Si3230
1 V
REN
)
+
and
I
OS
OVR
31
to
is

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